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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-11-20 11:03:13 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-12-01 05:50:52 +0100 |
| commit | 187543c90da824198a7da2b531665f4d2dece243 (patch) | |
| tree | 48ac0247b7f86f2a289bb6e15d3247f1dbd8467f /src/northbridge/amd/pi/00670F00/Kconfig | |
| parent | cc37bbd7acaaa060fa272115aa077baabac402c4 (diff) | |
AMD binaryPI: Switch to MMCONF_SUPPORT_DEFAULT
Vendorcode always does PCI MMCONF access once it is
enabled via MSR.
In coreboot proper, we don't give opportunity to make
pci_read/write calls before PCI MMCONF is enabled via MSR.
This happens early in romstage amd_initmmio() for all cores.
Change-Id: Id6ec25706b52441259e7dc1582f9a4ce8b154083
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17534
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge/amd/pi/00670F00/Kconfig')
| -rw-r--r-- | src/northbridge/amd/pi/00670F00/Kconfig | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/northbridge/amd/pi/00670F00/Kconfig b/src/northbridge/amd/pi/00670F00/Kconfig index e349635bae..a92658a098 100644 --- a/src/northbridge/amd/pi/00670F00/Kconfig +++ b/src/northbridge/amd/pi/00670F00/Kconfig @@ -14,7 +14,6 @@ ## config NORTHBRIDGE_AMD_PI_00670F00 bool - select MMCONF_SUPPORT if NORTHBRIDGE_AMD_PI_00670F00 |