diff options
author | Bruce Griffith <Bruce.Griffith@se-eng.com> | 2014-10-22 03:33:49 -0600 |
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committer | Dave Frodin <dave.frodin@se-eng.com> | 2015-03-10 16:43:23 +0100 |
commit | 006364eeddf763cddc5f63e738dadc52355bbe9a (patch) | |
tree | 0e3f1aee2d498fc78711ecff11a8ff0a666e6d79 /src/northbridge/amd/pi/00630F01/pci_devs.h | |
parent | 1a7da5c3ee4e2492dd021cefdcc72ab17c85f164 (diff) |
AMD Bald Eagle: Add northbridge files for new AMD processor
Also fix a typo in a config option for SteppeEagle.
Change-Id: Iad51cc917217aa0eac751dc805c304652d20e066
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/7247
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/northbridge/amd/pi/00630F01/pci_devs.h')
-rw-r--r-- | src/northbridge/amd/pi/00630F01/pci_devs.h | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/src/northbridge/amd/pi/00630F01/pci_devs.h b/src/northbridge/amd/pi/00630F01/pci_devs.h new file mode 100644 index 0000000000..4680621414 --- /dev/null +++ b/src/northbridge/amd/pi/00630F01/pci_devs.h @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _AMD_00630F01_PCI_DEVS_H_ +#define _AMD_00630F01_PCI_DEVS_H_ + +#define BUS0 0 + +/* Graphics and Display */ +#define GFX_DEV 0x1 +#define GFX_FUNC 0 +#define GFX_DEVID 0x1304 +#define GFX_DEVFN PCI_DEVFN(GFX_DEV,GFX_FUNC) +#define PIRQ_GFX FCH_INT_TABLE_SIZE + /* Integrated graphics device, must be after the + * last C00/C01 entry + */ + +/* Internal Audio controller */ +#define ACTL_DEV 0x1 +#define ACTL_FUNC 1 +#define ACTL_DEVID 0x1308 +#define ACTL_DEVFN PCI_DEVFN(ACTL_DEV,ACTL_FUNC) +#define PIRQ_ACTL FCH_INT_TABLE_SIZE+1 + /* Integrated HDMI audio device, must be after the + * last C00/C01 entry + */ + +/* PCIe Ports */ +#define NB_GFX_PCIE_PORTS_DEV 0x2 +#define NB_GPP_PCIE_PORTS_DEV 0x3 +#define NB_PCIE_PORT1_DEVFN PCI_DEVFN(NB_GFX_PCIE_PORTS_DEV,0x01) +#define NB_PCIE_PORT2_DEVFN PCI_DEVFN(NB_GFX_PCIE_PORTS_DEV,0x02) +#define NB_PCIE_PORT3_DEVFN PCI_DEVFN(NB_GPP_PCIE_PORTS_DEV,0x01) +#define NB_PCIE_PORT4_DEVFN PCI_DEVFN(NB_GPP_PCIE_PORTS_DEV,0x02) +#define NB_PCIE_PORT5_DEVFN PCI_DEVFN(NB_GPP_PCIE_PORTS_DEV,0x03) +#define NB_PCIE_PORT6_DEVFN PCI_DEVFN(NB_GPP_PCIE_PORTS_DEV,0x04) +#define NB_PCIE_PORT7_DEVFN PCI_DEVFN(NB_GPP_PCIE_PORTS_DEV,0x05) + +#endif /* _AMD_00630F01_PCI_DEVS_H_ */ |