diff options
| author | Patrick Georgi <patrick@georgi-clan.de> | 2012-07-13 19:06:22 +0200 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2012-07-26 21:33:31 +0200 |
| commit | 7dc2864be7fcc342bab0c167997803f5faf147a1 (patch) | |
| tree | bf94e8694da70ef352eca13a04945e0ddc7c5e70 /src/northbridge/amd/lx | |
| parent | 1b3207ee617c24fd283e654359c20c88d95a69c8 (diff) | |
amd/lx: Move configuration from source to Kconfig
LX has two values that are usually automatically derived but can
be overridden, that were so far defined in each board's romstage.
These values, along with the toggle to enable override are now
part of LX's Kconfig. For boards that gave values but requested
autogeneration, the values are removed.
Further improvements: Figure out the various fields in PLLMSRlo
and make them sensible Kconfig options (instead of the hex value
it is now)
Change-Id: I8a17c89e4a3cb1b52aaceef645955ab7817b482d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1227
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/northbridge/amd/lx')
| -rw-r--r-- | src/northbridge/amd/lx/Kconfig | 31 | ||||
| -rw-r--r-- | src/northbridge/amd/lx/pll_reset.c | 8 |
2 files changed, 34 insertions, 5 deletions
diff --git a/src/northbridge/amd/lx/Kconfig b/src/northbridge/amd/lx/Kconfig index c1fea495ff..d74d71554a 100644 --- a/src/northbridge/amd/lx/Kconfig +++ b/src/northbridge/amd/lx/Kconfig @@ -2,7 +2,36 @@ config NORTHBRIDGE_AMD_LX bool select GEODE_VSA +if NORTHBRIDGE_AMD_LX + config VIDEO_MB int default 8 - depends on NORTHBRIDGE_AMD_LX + +config PLL_MANUAL_CONFIG + bool + +if PLL_MANUAL_CONFIG + +# "Core/GLIU Frequency" +config CORE_GLIU_500_266 + bool # "500MHz / 266MHz" + +config CORE_GLIU_500_333 + bool # "500MHz / 333MHz" + +config CORE_GLIU_500_400 + bool # "500MHz / 400MHz" + +config PLLMSRhi + hex + default 0x39c if CORE_GLIU_500_266 + default 0x49c if CORE_GLIU_500_333 + default 0x59c if CORE_GLIU_500_400 + +config PLLMSRlo + hex + +endif + +endif diff --git a/src/northbridge/amd/lx/pll_reset.c b/src/northbridge/amd/lx/pll_reset.c index 3077b61c9c..bf01e54e29 100644 --- a/src/northbridge/amd/lx/pll_reset.c +++ b/src/northbridge/amd/lx/pll_reset.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -static void pll_reset(char manualconf) +static void pll_reset(void) { msr_t msrGlcpSysRstpll; @@ -31,13 +31,13 @@ static void pll_reset(char manualconf) if (!(msrGlcpSysRstpll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))) { printk(BIOS_DEBUG, "Configuring PLL.\n"); - if (manualconf) { + if (CONFIG_PLL_MANUAL_CONFIG) { post_code(POST_PLL_MANUAL); /* CPU and GLIU mult/div (GLMC_CLK = GLIU_CLK / 2) */ - msrGlcpSysRstpll.hi = PLLMSRhi; + msrGlcpSysRstpll.hi = CONFIG_PLLMSRhi; /* Hold Count - how long we will sit in reset */ - msrGlcpSysRstpll.lo = PLLMSRlo; + msrGlcpSysRstpll.lo = CONFIG_PLLMSRlo; } else { /*automatic configuration (straps) */ post_code(POST_PLL_STRAP); |