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authorElyes HAOUAS <ehaouas@noos.fr>2018-08-09 18:55:58 +0200
committerMartin Roth <martinroth@google.com>2018-08-10 21:25:53 +0000
commit3d45000c9cab2e5e5cac11a0a6af9abdce8aa80d (patch)
tree7b5096ca1f81fecf70418020aba184e446f995e0 /src/northbridge/amd/lx
parent1895838e7a3807a6fce324f0dfed193a3821f6df (diff)
src: Fix typo
Change-Id: I689c5663ef59861f79b68220abd146144f7618de Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/amd/lx')
-rw-r--r--src/northbridge/amd/lx/northbridgeinit.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c
index 6c2efb320c..c7db156ceb 100644
--- a/src/northbridge/amd/lx/northbridgeinit.c
+++ b/src/northbridge/amd/lx/northbridgeinit.c
@@ -122,7 +122,7 @@ static void SysmemInit(struct gliutable *gl)
int sizembytes, sizebytes;
/*
- * Figure out how much RAM is in the machine and alocate all to the
+ * Figure out how much RAM is in the machine and allocate all to the
* system. We will adjust for SMM now and Frame Buffer later.
*/
sizembytes = sizeram();
@@ -272,7 +272,7 @@ static void GLPCIInit(void)
* base of 1M and top of around 256M
*/
/* we have to create a page-aligned (4KB page) address for base and top */
- /* So we need a high page aligned addresss (pah) and low page aligned address (pal)
+ /* So we need a high page aligned address (pah) and low page aligned address (pal)
* pah is from msr.hi << 12 | msr.low >> 20. pal is msr.lo << 12
*/
pah = ((msr.hi & 0xFF) << 12) | ((msr.lo >> 20) & 0xFFF);