From 3d45000c9cab2e5e5cac11a0a6af9abdce8aa80d Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 9 Aug 2018 18:55:58 +0200 Subject: src: Fix typo Change-Id: I689c5663ef59861f79b68220abd146144f7618de Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/27988 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/northbridge/amd/lx/northbridgeinit.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/northbridge/amd/lx') diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c index 6c2efb320c..c7db156ceb 100644 --- a/src/northbridge/amd/lx/northbridgeinit.c +++ b/src/northbridge/amd/lx/northbridgeinit.c @@ -122,7 +122,7 @@ static void SysmemInit(struct gliutable *gl) int sizembytes, sizebytes; /* - * Figure out how much RAM is in the machine and alocate all to the + * Figure out how much RAM is in the machine and allocate all to the * system. We will adjust for SMM now and Frame Buffer later. */ sizembytes = sizeram(); @@ -272,7 +272,7 @@ static void GLPCIInit(void) * base of 1M and top of around 256M */ /* we have to create a page-aligned (4KB page) address for base and top */ - /* So we need a high page aligned addresss (pah) and low page aligned address (pal) + /* So we need a high page aligned address (pah) and low page aligned address (pal) * pah is from msr.hi << 12 | msr.low >> 20. pal is msr.lo << 12 */ pah = ((msr.hi & 0xFF) << 12) | ((msr.lo >> 20) & 0xFFF); -- cgit v1.2.3