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authorElyes HAOUAS <ehaouas@noos.fr>2016-09-19 10:27:57 -0600
committerPatrick Georgi <pgeorgi@google.com>2016-09-21 11:04:45 +0200
commita813160fbc37c41451afa01667669cf81b5799e7 (patch)
tree7792923bc839371a72c012bd520cba0cbf019534 /src/northbridge/amd/lx/northbridge.c
parent6fcfd919f1f6231bb03eefcff01cc39cb18abb90 (diff)
northbridge/amd: Improve code formatting
Change-Id: I80a2753f22d5211c8be4e17e2338402286a2cadc Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16645 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge/amd/lx/northbridge.c')
-rw-r--r--src/northbridge/amd/lx/northbridge.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c
index 2ba4a0415d..a40a628187 100644
--- a/src/northbridge/amd/lx/northbridge.c
+++ b/src/northbridge/amd/lx/northbridge.c
@@ -91,7 +91,7 @@ struct msr_defaults {
/* 180d is left at default, e0000-fffff is non-cached */
/* we will assume 180e, the ssm region configuration, is left at default or set by VSM */
/* we will not set 0x180f, the DMM,yet */
- //{0x1810, {.hi=0xee7ff000, .lo=RRCF_LOW(0xee000000, WRITE_COMBINE|CACHE_DISABLE)}},
+ //{0x1810, {.hi = 0xee7ff000, .lo = RRCF_LOW(0xee000000, WRITE_COMBINE|CACHE_DISABLE)}},
//{0x1811, {.hi = 0xefffb000, .lo = RRCF_LOW_CD(0xefff8000)}},
//{0x1812, {.hi = 0xefff7000, .lo = RRCF_LOW_CD(0xefff4000)}},
//{0x1813, {.hi = 0xefff3000, .lo = RRCF_LOW_CD(0xefff0000)}},