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authorElyes HAOUAS <ehaouas@noos.fr>2016-09-19 10:27:57 -0600
committerPatrick Georgi <pgeorgi@google.com>2016-09-21 11:04:45 +0200
commita813160fbc37c41451afa01667669cf81b5799e7 (patch)
tree7792923bc839371a72c012bd520cba0cbf019534 /src/northbridge/amd/gx2
parent6fcfd919f1f6231bb03eefcff01cc39cb18abb90 (diff)
northbridge/amd: Improve code formatting
Change-Id: I80a2753f22d5211c8be4e17e2338402286a2cadc Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16645 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge/amd/gx2')
-rw-r--r--src/northbridge/amd/gx2/northbridgeinit.c90
-rw-r--r--src/northbridge/amd/gx2/pll_reset.c6
-rw-r--r--src/northbridge/amd/gx2/raminit.c12
3 files changed, 54 insertions, 54 deletions
diff --git a/src/northbridge/amd/gx2/northbridgeinit.c b/src/northbridge/amd/gx2/northbridgeinit.c
index f21d717a55..3b020165b3 100644
--- a/src/northbridge/amd/gx2/northbridgeinit.c
+++ b/src/northbridge/amd/gx2/northbridgeinit.c
@@ -35,24 +35,24 @@ struct gliutable
};
struct gliutable gliu0table[] = {
- {.desc_name=GLIU0_P2D_BM_0, .desc_type= BM,.hi= MSR_MC + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */
- {.desc_name=GLIU0_P2D_BM_1, .desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc */
- {.desc_name=GLIU0_P2D_SC_0, .desc_type= SC_SHADOW,.hi= MSR_MC + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */
- {.desc_name=GLIU0_P2D_R_0, .desc_type= R_SYSMEM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */
- {.desc_name=GLIU0_P2D_BMO_0, .desc_type= BMO_SMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */
- {.desc_name=GLIU0_GLD_MSR_COH, .desc_type= OTHER,.hi= 0x0,.lo= GL0_CPU},
- {.desc_name=GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0},
+ {.desc_name = GLIU0_P2D_BM_0, .desc_type= BM,.hi= MSR_MC + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */
+ {.desc_name = GLIU0_P2D_BM_1, .desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc */
+ {.desc_name = GLIU0_P2D_SC_0, .desc_type= SC_SHADOW,.hi= MSR_MC + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */
+ {.desc_name = GLIU0_P2D_R_0, .desc_type= R_SYSMEM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */
+ {.desc_name = GLIU0_P2D_BMO_0, .desc_type= BMO_SMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */
+ {.desc_name = GLIU0_GLD_MSR_COH, .desc_type= OTHER,.hi= 0x0,.lo= GL0_CPU},
+ {.desc_name = GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0},
};
struct gliutable gliu1table[] = {
- {.desc_name=GLIU1_P2D_BM_0, .desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */
- {.desc_name=GLIU1_P2D_BM_1, .desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= (0x80 << 20) + 0x0FFFE0},/* 80000-9ffff to Mc */
- {.desc_name=GLIU1_P2D_SC_0, .desc_type= SC_SHADOW,.hi= MSR_GL0 + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) */
- {.desc_name=GLIU1_P2D_R_0, .desc_type= R_SYSMEM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */
- {.desc_name=GLIU1_P2D_BM_3, .desc_type= BM_SMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */
- {.desc_name=GLIU1_GLD_MSR_COH, .desc_type= OTHER,.hi= 0x0,.lo= GL1_GLIU0},
- {.desc_name=GLIU1_IOD_SC_0, .desc_type= SCIO,.hi= (GL1_GLCP << 29) + 0x0,.lo= 0x033000F0}, /* FooGlue FPU 0xF0 */
- {.desc_name=GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0},
+ {.desc_name = GLIU1_P2D_BM_0, .desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */
+ {.desc_name = GLIU1_P2D_BM_1, .desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= (0x80 << 20) + 0x0FFFE0},/* 80000-9ffff to Mc */
+ {.desc_name = GLIU1_P2D_SC_0, .desc_type= SC_SHADOW,.hi= MSR_GL0 + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) */
+ {.desc_name = GLIU1_P2D_R_0, .desc_type= R_SYSMEM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */
+ {.desc_name = GLIU1_P2D_BM_3, .desc_type= BM_SMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */
+ {.desc_name = GLIU1_GLD_MSR_COH, .desc_type= OTHER,.hi= 0x0,.lo= GL1_GLIU0},
+ {.desc_name = GLIU1_IOD_SC_0, .desc_type= SCIO,.hi= (GL1_GLCP << 29) + 0x0,.lo= 0x033000F0}, /* FooGlue FPU 0xF0 */
+ {.desc_name = GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0},
};
struct gliutable *gliutables[] = { gliu0table, gliu1table, 0 };
@@ -64,51 +64,51 @@ struct msrinit
};
struct msrinit ClockGatingDefault[] = {
- {GLIU0_GLD_MSR_PM, {.hi=0x00,.lo=0x0005}},
+ {GLIU0_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0005}},
/* MC must stay off in SDR mode. It is turned on in CPUBug??? lotus #77.142 */
- {MC_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}},
- {GLIU1_GLD_MSR_PM, {.hi=0x00,.lo=0x0005}},
- {VG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* lotus #77.163 */
- {GP_GLD_MSR_PM, {.hi=0x00,.lo=0x0001}},
- {DF_GLD_MSR_PM, {.hi=0x00,.lo=0x0155}},
- {GLCP_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}},
- {GLPCI_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}},
- {FG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* Always on */
+ {MC_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0000}},
+ {GLIU1_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0005}},
+ {VG_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0000}}, /* lotus #77.163 */
+ {GP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0001}},
+ {DF_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0155}},
+ {GLCP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}},
+ {GLPCI_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}},
+ {FG_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0000}}, /* Always on */
{0xffffffff, {0xffffffff, 0xffffffff}},
};
/* All On */
struct msrinit ClockGatingAllOn[] = {
- {GLIU0_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}},
- {MC_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}},
- {GLIU1_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}},
- {VG_GLD_MSR_PM, {.hi=0x00, .lo=0x00}},
- {GP_GLD_MSR_PM, {.hi=0x00,.lo=0x000000001}},
- {DF_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}},
- {GLCP_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}},
- {GLPCI_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}},
- {FG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}},
+ {GLIU0_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0FFFFFFFF}},
+ {MC_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0FFFFFFFF}},
+ {GLIU1_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0FFFFFFFF}},
+ {VG_GLD_MSR_PM, {.hi = 0x00, .lo = 0x00}},
+ {GP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x000000001}},
+ {DF_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0FFFFFFFF}},
+ {GLCP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0FFFFFFFF}},
+ {GLPCI_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0FFFFFFFF}},
+ {FG_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0000}},
{0xffffffff, {0xffffffff, 0xffffffff}},
};
/* Performance */
struct msrinit ClockGatingPerformance[] = {
- {VG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* lotus #77.163 */
- {GP_GLD_MSR_PM, {.hi=0x00,.lo=0x0001}},
- {DF_GLD_MSR_PM, {.hi=0x00,.lo=0x0155}},
- {GLCP_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}},
+ {VG_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0000}}, /* lotus #77.163 */
+ {GP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0001}},
+ {DF_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0155}},
+ {GLCP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}},
{0xffffffff, {0xffffffff, 0xffffffff}},
};
/* SET GeodeLink PRIORITY */
struct msrinit GeodeLinkPriorityTable[] = {
- {CPU_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0220}}, /* CPU Priority. */
- {DF_GLD_MSR_MASTER_CONF, {.hi=0x00,.lo=0x0000}}, /* DF Priority. */
- {VG_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0720}}, /* VG Primary and Secondary Priority. */
- {GP_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0010}}, /* Graphics Priority. */
- {GLPCI_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0027}}, /* GLPCI Priority + PID */
- {GLCP_GLD_MSR_CONF, {.hi=0x00,.lo=0x0001}}, /* GLCP Priority + PID */
- {FG_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0622}}, /* FG PID */
+ {CPU_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0220}}, /* CPU Priority. */
+ {DF_GLD_MSR_MASTER_CONF, {.hi = 0x00,.lo = 0x0000}}, /* DF Priority. */
+ {VG_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0720}}, /* VG Primary and Secondary Priority. */
+ {GP_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0010}}, /* Graphics Priority. */
+ {GLPCI_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0027}}, /* GLPCI Priority + PID */
+ {GLCP_GLD_MSR_CONF, {.hi = 0x00,.lo = 0x0001}}, /* GLCP Priority + PID */
+ {FG_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0622}}, /* FG PID */
{0x0FFFFFFFF, {0x0FFFFFFFF, 0x0FFFFFFFF}}, /* END */
};
@@ -422,7 +422,7 @@ static uint64_t getShadow(void)
msr_t msr = { 0, 0 };
msr = rdmsr(GLIU0_P2D_SC_0);
- return ( ( (uint64_t) msr.hi ) << 32 ) | msr.lo;
+ return (((uint64_t) msr.hi) << 32) | msr.lo;
}
/* Set the cache RConf registers for the memory hole.
diff --git a/src/northbridge/amd/gx2/pll_reset.c b/src/northbridge/amd/gx2/pll_reset.c
index 303d64a108..0bae76dda0 100644
--- a/src/northbridge/amd/gx2/pll_reset.c
+++ b/src/northbridge/amd/gx2/pll_reset.c
@@ -88,7 +88,7 @@ static void pll_reset(void)
wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
/* If the "we've already been here" flag is set, don't reconfigure the pll */
- if ( !(msrGlcpSysRstpll.lo & PLLCHECK_COMPLETED ) )
+ if (!(msrGlcpSysRstpll.lo & PLLCHECK_COMPLETED))
{ /* we haven't configured the PLL; do it now */
/* Store PCI33(0)/66(1), SDR(0)/DDR(1), and CRT(0)/TFT(1) in upper esi to get to the */
@@ -145,8 +145,8 @@ static void pll_reset(void)
/* CheckPCIsync: */
/* If FBdiv/Mdiv is evenly divisible then set the PCI semi-sync. FB is always greater */
/* look up the real divider... if we get a 0 we have serious problems */
- if ( !(fbdiv2plldiv[((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_FBDIV_SHIFT) & 0x3f)] %
- (((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_MDIV_SHIFT) & 0x0F) + 2)) )
+ if (!(fbdiv2plldiv[((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_FBDIV_SHIFT) & 0x3f)] %
+ (((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_MDIV_SHIFT) & 0x0F) + 2)))
{
SyncBits |= RSTPPL_LOWER_PCI_SEMI_SYNC_SET;
}
diff --git a/src/northbridge/amd/gx2/raminit.c b/src/northbridge/amd/gx2/raminit.c
index db10138b34..6e66d7dcf5 100644
--- a/src/northbridge/amd/gx2/raminit.c
+++ b/src/northbridge/amd/gx2/raminit.c
@@ -97,7 +97,7 @@ static void auto_size_dimm(unsigned int dimm)
dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1; /* shift to multiply by # DIMM banks */
printk(BIOS_DEBUG, "BEFORT CTZ\n");
dimm_size = __builtin_ctz(dimm_size);
- printk(BIOS_DEBUG, "TEST DIMM SIZE>7\n");
+ printk(BIOS_DEBUG, "TEST DIMM SIZE > 7\n");
if (dimm_size > 7) { /* 7 is 512MB only support 512MB per DIMM */
printk(BIOS_EMERG, "Only support up to 512MB per DIMM\n");
post_code(ERROR_DENSITY_DIMM);
@@ -130,7 +130,7 @@ static void auto_size_dimm(unsigned int dimm)
* Remember that pa[2:0] are zeroed out since it's a 64-bit data bus (8 bytes),
* so lower 3 address bits are dont_cares. So from the table above,
* it's easier to see what the old code is doing: if for example,
- * #col_addr_bits=7(06h), it adds 3 to get 10, then does 2^10=1K.
+ * #col_addr_bits = 7(06h), it adds 3 to get 10, then does 2^10 = 1K.
*/
spd_byte = NumColAddr[spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF];
@@ -142,10 +142,10 @@ static void auto_size_dimm(unsigned int dimm)
}
printk(BIOS_DEBUG, ">11address test\n");
spd_byte -= 7;
- if (spd_byte > 4) { /* if the value is above 4 it means >11 col address lines */
- spd_byte = 7; /* which means >16k so set to disabled */
+ if (spd_byte > 4) { /* if the value is above 4 it means > 11 col address lines */
+ spd_byte = 7; /* which means > 16k so set to disabled */
}
- dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT; /* 0=1k,1=2k,2=4k,etc */
+ dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT; /* 0 = 1k, 1 = 2k, 2 = 4k, etc */
printk(BIOS_DEBUG, "RDMSR CF07\n");
msr = rdmsr(MC_CF07_DATA);
@@ -230,7 +230,7 @@ const uint8_t CASDDR[] = { 5, 5, 2, 6, 0 }; /* 1(1.5), 1.5, 2, 2.5, 0 */
static u8 getcasmap(u32 dimm, u16 glspeed)
{
u16 dimm_speed;
- u8 spd_byte, casmap, casmap_shift=0;
+ u8 spd_byte, casmap, casmap_shift = 0;
/************************** DIMM0 **********************************/
casmap = spd_read_byte(dimm, SPD_ACCEPTABLE_CAS_LATENCIES);