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authorElyes HAOUAS <ehaouas@noos.fr>2018-07-08 12:39:34 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-07-09 09:29:53 +0000
commitfd051dc018346e5947d9d8733e269fc5020236ba (patch)
treed12a70629b7565c20643c97ca8a933c4344e5b7b /src/northbridge/amd/amdmct
parent95bca33efa280e606f7c6d41541cec67c0eb227f (diff)
src/northbridge: Use "foo *bar" instead of "foo* bar"
Change-Id: Iaf86a0c91da089b486bd39518e5c8216163bf8ec Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/northbridge/amd/amdmct')
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mct_d.h10
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c4
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c18
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/s3utils.c42
4 files changed, 37 insertions, 37 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
index a02f49b5c6..3cda13fd35 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
@@ -1055,13 +1055,13 @@ void mct_EnableDatIntlv_D(struct MCTStatStruc *pMCTstat,
void SetDllSpeedUp_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat, u8 dct);
uint8_t get_available_lane_count(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat);
-void read_dqs_receiver_enable_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg);
-void read_dqs_write_timing_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg);
+void read_dqs_receiver_enable_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg);
+void read_dqs_write_timing_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg);
void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t enable);
-void read_dqs_read_data_timing_registers(uint16_t* delay, uint32_t dev,
+void read_dqs_read_data_timing_registers(uint16_t *delay, uint32_t dev,
uint8_t dct, uint8_t dimm, uint32_t index_reg);
-void write_dqs_read_data_timing_registers(uint16_t* delay, uint32_t dev,
+void write_dqs_read_data_timing_registers(uint16_t *delay, uint32_t dev,
uint8_t dct, uint8_t dimm, uint32_t index_reg);
void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat);
@@ -1133,7 +1133,7 @@ void write_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat,
void read_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat, uint8_t dct,
uint8_t Receiver, uint8_t lane, uint8_t stop_on_error);
-void write_dqs_receiver_enable_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg);
+void write_dqs_receiver_enable_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg);
uint32_t fenceDynTraining_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat, uint8_t dct);
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
index 9b7481717d..04299937d8 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
@@ -317,7 +317,7 @@ static void CalcEccDQSPos_D(struct MCTStatStruc *pMCTstat,
pDCTstat->DQSDelay = (u8)DQSDelay;
}
-static void read_dqs_write_data_timing_registers(uint16_t* delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)
+static void read_dqs_write_data_timing_registers(uint16_t *delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)
{
uint32_t dword;
uint32_t mask;
@@ -346,7 +346,7 @@ static void read_dqs_write_data_timing_registers(uint16_t* delay, uint32_t dev,
delay[8] = dword & mask;
}
-static void write_dqs_write_data_timing_registers(uint16_t* delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)
+static void write_dqs_write_data_timing_registers(uint16_t *delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)
{
uint32_t dword;
uint32_t mask;
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
index 7c3781fb40..bae2e8998a 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
@@ -255,7 +255,7 @@ static uint16_t fam15_receiver_enable_training_seed(struct DCTStatStruc *pDCTsta
return seed;
}
-void read_dqs_write_timing_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)
+void read_dqs_write_timing_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)
{
uint8_t lane;
uint32_t dword;
@@ -282,7 +282,7 @@ void read_dqs_write_timing_control_registers(uint16_t* current_total_delay, uint
}
#ifdef UNUSED_CODE
-static void write_dqs_write_timing_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)
+static void write_dqs_write_timing_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)
{
uint8_t lane;
uint32_t dword;
@@ -314,7 +314,7 @@ static void write_dqs_write_timing_control_registers(uint16_t* current_total_del
}
#endif
-static void write_write_data_timing_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)
+static void write_write_data_timing_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)
{
uint8_t lane;
uint32_t dword;
@@ -353,7 +353,7 @@ static void write_write_data_timing_control_registers(uint16_t* current_total_de
}
}
-void read_dqs_receiver_enable_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)
+void read_dqs_receiver_enable_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)
{
uint8_t lane;
uint32_t mask;
@@ -387,7 +387,7 @@ void read_dqs_receiver_enable_control_registers(uint16_t* current_total_delay, u
}
}
-void write_dqs_receiver_enable_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)
+void write_dqs_receiver_enable_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)
{
uint8_t lane;
uint32_t mask;
@@ -424,7 +424,7 @@ void write_dqs_receiver_enable_control_registers(uint16_t* current_total_delay,
}
}
-static void read_dram_phase_recovery_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)
+static void read_dram_phase_recovery_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)
{
uint8_t lane;
uint32_t dword;
@@ -456,7 +456,7 @@ static void read_dram_phase_recovery_control_registers(uint16_t* current_total_d
}
}
-static void write_dram_phase_recovery_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)
+static void write_dram_phase_recovery_control_registers(uint16_t *current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)
{
uint8_t lane;
uint32_t dword;
@@ -494,7 +494,7 @@ static void write_dram_phase_recovery_control_registers(uint16_t* current_total_
}
}
-void read_dqs_read_data_timing_registers(uint16_t* delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)
+void read_dqs_read_data_timing_registers(uint16_t *delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)
{
uint8_t shift;
uint32_t dword;
@@ -528,7 +528,7 @@ void read_dqs_read_data_timing_registers(uint16_t* delay, uint32_t dev, uint8_t
delay[8] = (dword & mask) >> shift;
}
-void write_dqs_read_data_timing_registers(uint16_t* delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)
+void write_dqs_read_data_timing_registers(uint16_t *delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg)
{
uint8_t shift;
uint32_t dword;
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
index 84e26eadea..4c33a2fb35 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
@@ -194,11 +194,11 @@ uint16_t calculate_nvram_mct_hash(void)
return ret;
}
-static struct amd_s3_persistent_data * map_s3nv_in_nvram(void)
+static struct amd_s3_persistent_data *map_s3nv_in_nvram(void)
{
ssize_t s3nv_offset;
ssize_t s3nv_file_offset;
- void * s3nv_cbfs_file_ptr;
+ void *s3nv_cbfs_file_ptr;
struct amd_s3_persistent_data *persistent_data;
/* Obtain CBFS file offset */
@@ -269,7 +269,7 @@ static uint32_t read_config32_dct_nbpstate(struct device *dev, uint8_t node,
return pci_read_config32(dev, reg);
}
-static void copy_cbmem_spd_data_to_save_variable(struct amd_s3_persistent_data* persistent_data, uint8_t * restored)
+static void copy_cbmem_spd_data_to_save_variable(struct amd_s3_persistent_data *persistent_data, uint8_t *restored)
{
uint8_t node;
uint8_t dimm;
@@ -303,7 +303,7 @@ static void copy_cbmem_spd_data_to_save_variable(struct amd_s3_persistent_data*
}
}
-void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_data)
+void copy_mct_data_to_save_variable(struct amd_s3_persistent_data *persistent_data)
{
uint8_t i;
uint8_t j;
@@ -326,7 +326,7 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_da
persistent_data->node[node].node_present = 1;
for (channel = 0; channel < 2; channel++) {
- struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];
+ struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];
/* Stage 1 */
data->f2x110 = pci_read_config32(dev_fn2, 0x110);
@@ -594,7 +594,7 @@ static void wrmsr_uint64_t(unsigned long index, uint64_t value) {
wrmsr(index, msr);
}
-void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persistent_data, uint8_t training_only)
+void restore_mct_data_from_save_variable(struct amd_s3_persistent_data *persistent_data, uint8_t training_only)
{
uint8_t i;
uint8_t j;
@@ -608,7 +608,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste
/* Only restore the Receiver Enable and DQS training registers */
for (node = 0; node < MAX_NODES_SUPPORTED; node++) {
for (channel = 0; channel < 2; channel++) {
- struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];
+ struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];
if (!persistent_data->node[node].node_present)
continue;
@@ -652,7 +652,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste
/* Stage 1 */
for (node = 0; node < MAX_NODES_SUPPORTED; node++) {
for (channel = 0; channel < 2; channel++) {
- struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];
+ struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];
if (!persistent_data->node[node].node_present)
continue;
@@ -663,7 +663,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste
/* Stage 2 */
for (node = 0; node < MAX_NODES_SUPPORTED; node++) {
for (channel = 0; channel < 2; channel++) {
- struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];
+ struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];
if (!persistent_data->node[node].node_present)
continue;
@@ -719,7 +719,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste
/* Stage 3 */
for (node = 0; node < MAX_NODES_SUPPORTED; node++) {
for (channel = 0; channel < 2; channel++) {
- struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];
+ struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];
if (!persistent_data->node[node].node_present)
continue;
@@ -758,7 +758,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste
if (is_fam15h()) {
for (node = 0; node < MAX_NODES_SUPPORTED; node++) {
for (channel = 0; channel < 2; channel++) {
- struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];
+ struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];
if (!persistent_data->node[node].node_present)
continue;
@@ -823,7 +823,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste
/* Stage 4 */
for (node = 0; node < MAX_NODES_SUPPORTED; node++) {
for (channel = 0; channel < 2; channel++) {
- struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];
+ struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];
if (!persistent_data->node[node].node_present)
continue;
@@ -868,7 +868,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste
/* Stage 5 */
for (node = 0; node < MAX_NODES_SUPPORTED; node++) {
for (channel = 0; channel < 2; channel++) {
- struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];
+ struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];
if (!persistent_data->node[node].node_present)
continue;
@@ -909,7 +909,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste
/* Stage 6 */
for (node = 0; node < MAX_NODES_SUPPORTED; node++) {
for (channel = 0; channel < 2; channel++) {
- struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];
+ struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];
if (!persistent_data->node[node].node_present)
continue;
@@ -926,7 +926,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste
if (is_fam15h()) {
for (node = 0; node < MAX_NODES_SUPPORTED; node++) {
for (channel = 0; channel < 2; channel++) {
- struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];
+ struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];
if (!persistent_data->node[node].node_present)
continue;
@@ -964,7 +964,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste
/* Stage 7 */
for (node = 0; node < MAX_NODES_SUPPORTED; node++) {
for (channel = 0; channel < 2; channel++) {
- struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];
+ struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];
if (!persistent_data->node[node].node_present)
continue;
@@ -983,7 +983,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste
/* Stage 8 */
for (node = 0; node < MAX_NODES_SUPPORTED; node++) {
for (channel = 0; channel < 2; channel++) {
- struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];
+ struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];
if (!persistent_data->node[node].node_present)
continue;
@@ -1010,7 +1010,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste
/* Stage 9 */
for (node = 0; node < MAX_NODES_SUPPORTED; node++) {
for (channel = 0; channel < 2; channel++) {
- struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];
+ struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];
if (!persistent_data->node[node].node_present)
continue;
@@ -1034,7 +1034,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste
/* Stage 10 */
for (node = 0; node < MAX_NODES_SUPPORTED; node++) {
for (channel = 0; channel < 2; channel++) {
- struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];
+ struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];
if (!persistent_data->node[node].node_present)
continue;
@@ -1066,7 +1066,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste
if (IS_ENABLED(CONFIG_DIMM_DDR3)) {
for (node = 0; node < MAX_NODES_SUPPORTED; node++) {
for (channel = 0; channel < 2; channel++) {
- struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];
+ struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];
if (!persistent_data->node[node].node_present)
continue;
@@ -1081,7 +1081,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste
/* Other */
for (node = 0; node < MAX_NODES_SUPPORTED; node++) {
for (channel = 0; channel < 2; channel++) {
- struct amd_s3_persistent_mct_channel_data* data = &persistent_data->node[node].channel[channel];
+ struct amd_s3_persistent_mct_channel_data *data = &persistent_data->node[node].channel[channel];
if (!persistent_data->node[node].node_present)
continue;