diff options
| author | Martin Roth <martinroth@google.com> | 2016-01-15 10:20:11 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-02-02 14:37:09 +0100 |
| commit | 2f91403303a66c5e724761a74863e3452291b154 (patch) | |
| tree | 7269f212612416f263dfba9a50f88befe2015d70 /src/northbridge/amd/amdmct | |
| parent | bda8a04b0105f2b097b07fa336891af6981541cb (diff) | |
src: Fix various spelling and whitespace issues.
This fixes some spelling and whitespace issues that I came across
while working on various things in the tree.
There are no functional changes.
Change-Id: I33bc77282f2f94a1fc5f1bc713e44f72db20c1ab
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13016
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge/amd/amdmct')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h index 4de7af0de6..2bd39f9f4d 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h @@ -34,12 +34,12 @@ #define DCT_STATUS_LOAD_REDUCED 4 /* Load-Reduced DIMMs support */ #define DCT_STATUS_OnDimmMirror 24 /* OnDimmMirror support */ -/* PCI Defintions */ -#define FUN_HT 0 /* Funtion 0 Access */ -#define FUN_MAP 1 /* Funtion 1 Access */ -#define FUN_DCT 2 /* Funtion 2 Access */ -#define FUN_MISC 3 /* Funtion 3 Access */ -#define FUN_ADD_DCT 0xF /* Funtion 2 Additional Register Access */ +/* PCI Definitions */ +#define FUN_HT 0 /* Function 0 Access */ +#define FUN_MAP 1 /* Function 1 Access */ +#define FUN_DCT 2 /* Function 2 Access */ +#define FUN_MISC 3 /* Function 3 Access */ +#define FUN_ADD_DCT 0xF /* Function 2 Additional Register Access */ #define BOTH_DCTS 2 /* The access is independent of DCTs */ #define PCI_MIN_LOW 0 /* Lowest possible PCI register location */ #define PCI_MAX_HIGH 31 /* Highest possible PCI register location */ @@ -60,7 +60,7 @@ #define DRAM_CONT_ADD_ECC_PHASE_REC_CTRL 0x52 #define DRAM_CONT_ADD_WRITE_LEV_ERROR_REG 0x53 -/* CPU Register defintions */ +/* CPU Register definitions */ /* Register Bit Location */ #define DctAccessDone 31 @@ -155,7 +155,7 @@ typedef struct _sDCTStruct u8 ErrStatus[MAX_ERRORS]; /* Minor Error codes for DCT0 and 1 */ u8 DimmValid[MAX_TOTAL_DIMMS]; /* Indicates which DIMMs are valid for */ /* Total Number of DIMMs(per Node) */ - u8 WLTotalDelay[MAX_BYTE_LANES];/* Write Levelization Toral Delay */ + u8 WLTotalDelay[MAX_BYTE_LANES];/* Write Levelization Total Delay */ /* per byte lane */ u8 MaxDimmsInstalled; /* Max Dimms Installed for current DCT */ u8 DimmRanks[MAX_TOTAL_DIMMS]; /* Total Number of Ranks(per Dimm) */ |