diff options
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-06-04 00:11:03 -0500 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2015-11-11 06:14:20 +0100 |
| commit | df1fb9c05f822b5a84c802617d3bad7d049dcd76 (patch) | |
| tree | eb4fc73a5365d91f4702b15342d67581eed0a0e6 /src/northbridge/amd/amdmct/wrappers | |
| parent | 1b708656b2f347ab05bd89643322f86b7110a814 (diff) | |
amd/amdmct/mct_ddr3: Use training values from previous boot if possible
DRAM training accounts for most of the romstage startup time, yet
if the hardware configuration has not changed from the previous boot
the previously discovered training values are still valid. Use them
if the DIMM configuration has not changed since the last boot.
The SPD values of all installed DIMMs are hashed and stored in the S3
resume data area of the main system Flash device. If a DIMM is changed
the hash will almost certainly change as well, forcing retraining on next
boot.
Change-Id: I37ed277b16476d38e4af76c6ae827a575c6b017d
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11976
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/wrappers')
| -rw-r--r-- | src/northbridge/amd/amdmct/wrappers/mcti_d.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index 48ab8007ab..a030f71e95 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -396,14 +396,18 @@ static void mctHookAfterCPU(void) } +#if IS_ENABLED(CONFIG_DIMM_DDR2) static void mctSaveDQSSigTmg_D(void) { } +#endif +#if IS_ENABLED(CONFIG_DIMM_DDR2) static void mctGetDQSSigTmg_D(void) { } +#endif static void mctHookBeforeECC(void) |