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authorElyes HAOUAS <ehaouas@noos.fr>2018-08-07 12:16:56 +0200
committerMartin Roth <martinroth@google.com>2018-08-09 15:51:10 +0000
commit64f6b71af5443ac4e1126dc5f5202a1bc8657b31 (patch)
treea9dd78971edaf050f8a215332755b1a0f55d6cf1 /src/northbridge/amd/amdmct/mct_ddr3
parentbc0ec507f2183e28c9b45c34c46ce93ca070aed6 (diff)
src/northbridge: Fix typo
Change-Id: I00094028036f33892362b935899e1bceef1da625 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3')
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/s3utils.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
index 4c33a2fb35..388f064848 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
@@ -846,7 +846,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data *persiste
dword &= (0x1 << 7);
write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x94, dword);
- /* Restore DRAM Adddress/Timing Control Register */
+ /* Restore DRAM Address/Timing Control Register */
write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x04, data->f2x9cx04);
} else {
/* Disable PHY auto-compensation engine */