aboutsummaryrefslogtreecommitdiff
path: root/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c
diff options
context:
space:
mode:
authorElyes HAOUAS <ehaouas@noos.fr>2016-09-19 10:25:41 -0600
committerPatrick Georgi <pgeorgi@google.com>2016-09-21 16:49:15 +0200
commite1606731b63bedd12398acb57a115aa5d280811e (patch)
tree8da66e35adfc3142ae1eb822899abf039c975432 /src/northbridge/amd/amdmct/mct_ddr3/mctwl.c
parent8aa20193a6dc12ba6cf740b1ad41023475d69698 (diff)
northbridge/amd/amdmct: Improve code formatting
Change-Id: If87718b6c91d79212a9b045f5fda32d69ac4caee Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16643 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mctwl.c')
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mctwl.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c b/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c
index 44ea6e8f84..47c5004c0c 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c
@@ -426,7 +426,7 @@ void SetTargetFreq(struct MCTStatStruc *pMCTstat,
}
}
- /* wait for 500 MCLKs after ExitSelfRef, 500*2.5ns=1250ns */
+ /* wait for 500 MCLKs after ExitSelfRef, 500*2.5ns = 1250ns */
mct_Wait(250);
if (pDCTstat->Status & (1 << SB_Registered)) {
@@ -474,9 +474,9 @@ void Restore_OnDimmMirror(struct MCTStatStruc *pMCTstat,
{
if (pDCTstat->LogicalCPUID & (AMD_DR_Bx /* | AMD_RB_C0 */)) { /* We dont support RB-C0 now */
if (pDCTstat->MirrPresU_NumRegR & 0x55)
- Modify_OnDimmMirror(pDCTstat, 0, 1); /* dct=0, set */
+ Modify_OnDimmMirror(pDCTstat, 0, 1); /* dct = 0, set */
if (pDCTstat->MirrPresU_NumRegR & 0xAA)
- Modify_OnDimmMirror(pDCTstat, 1, 1); /* dct=1, set */
+ Modify_OnDimmMirror(pDCTstat, 1, 1); /* dct = 1, set */
}
}
void Clear_OnDimmMirror(struct MCTStatStruc *pMCTstat,
@@ -484,8 +484,8 @@ void Clear_OnDimmMirror(struct MCTStatStruc *pMCTstat,
{
if (pDCTstat->LogicalCPUID & (AMD_DR_Bx /* | AMD_RB_C0 */)) { /* We dont support RB-C0 now */
if (pDCTstat->MirrPresU_NumRegR & 0x55)
- Modify_OnDimmMirror(pDCTstat, 0, 0); /* dct=0, clear */
+ Modify_OnDimmMirror(pDCTstat, 0, 0); /* dct = 0, clear */
if (pDCTstat->MirrPresU_NumRegR & 0xAA)
- Modify_OnDimmMirror(pDCTstat, 1, 0); /* dct=1, clear */
+ Modify_OnDimmMirror(pDCTstat, 1, 0); /* dct = 1, clear */
}
}