diff options
| author | Zheng Bao <zheng.bao@amd.com> | 2011-01-06 02:18:12 +0000 |
|---|---|---|
| committer | Zheng Bao <Zheng.Bao@amd.com> | 2011-01-06 02:18:12 +0000 |
| commit | 69436e1a8ccf50d67004f74360f3ff5e6a146b9a (patch) | |
| tree | a1765936b1304bcc16aaba9dafe7ead509cf50ec /src/northbridge/amd/amdmct/mct_ddr3/mctwl.c | |
| parent | da712f3f45bf27dc7326887c2d38cc7599f7448a (diff) | |
Fix some settings fo AMD MCT. It is based on BIOS test suite.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6246 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mctwl.c')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mctwl.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c b/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c index d4b531f3af..57d56814c1 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c @@ -351,7 +351,7 @@ static void Modify_OnDimmMirror(struct DCTStatStruc *pDCTstat, u8 dct, u8 set) { u32 val; u32 reg_off = dct * 0x100 + 0x44; - while (reg_off < 0x60) { + while (reg_off < (dct * 0x100 + 0x60)) { val = Get_NB32(pDCTstat->dev_dct, reg_off); if (val & (1 << CSEnable)) set ? (val |= 1 << onDimmMirror) : (val &= ~(1<<onDimmMirror)); |