diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-08-23 21:36:02 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-08-31 20:28:51 +0200 |
| commit | 5a7e72f1aef02b326a67d883d92fe8c0aad9f3a9 (patch) | |
| tree | 8d51ad99d2d9469f195694b29a571facf18d89f8 /src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c | |
| parent | 2b010b8795de84b6753c5e49d6a73c25fee96da1 (diff) | |
northbridge/amd: Add required space before opening parenthesis '('
Change-Id: Ic85f725bbdf72fbac5a4d9482c61343c5eb35e25
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16305
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c index c386fce087..2f4d4da82b 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c @@ -23,7 +23,7 @@ u8 mct_checkNumberOfDqsRcvEn_Pass(u8 pass) u32 SetupDqsPattern_PassA(u8 Pass) { u32 ret; - if(Pass == FirstPass) + if (Pass == FirstPass) ret = (u32) TestPattern1_D; else ret = (u32) TestPattern2_D; @@ -34,7 +34,7 @@ u32 SetupDqsPattern_PassA(u8 Pass) u32 SetupDqsPattern_PassB(u8 Pass) { u32 ret; - if(Pass == FirstPass) + if (Pass == FirstPass) ret = (u32) TestPattern0_D; else ret = (u32) TestPattern2_D; @@ -61,7 +61,7 @@ u8 mct_Get_Start_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, for ( i=0;i<bn; i++) { val = p[i]; - if(val > max) { + if (val > max) { max = val; } } @@ -91,7 +91,7 @@ u16 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, /* FIXME: which byte? */ p_1 = pDCTstat->B_RCVRDLY_1; /* p_1 = pDCTstat->CH_D_B_RCVRDLY_1[Channel][Receiver>>1]; */ - for(i=0; i<bn; i++) { + for (i=0; i<bn; i++) { val = p[i]; /* left edge */ if (val != (RcvrEnDlyLimit - 1)) { @@ -111,7 +111,7 @@ u16 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat, pDCTstat->DimmTrainFail &= ~(1<<(Receiver + Channel)); } } else { - for(i=0; i < bn; i++) { + for (i=0; i < bn; i++) { val = p[i]; /* Add 1/2 Memlock delay */ /* val += Pass1MemClkDly; */ |