diff options
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2016-01-30 23:34:51 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-02-05 22:26:31 +0100 |
| commit | 31682364ba062fb3cbf4ff3b0ad7cbdb7b5daae1 (patch) | |
| tree | 0824c0e09657c7fbbdc71c83e9bba0969826f7a9 /src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | |
| parent | 606b6ec686e07930008c5c1710efaaf3d097f465 (diff) | |
nb/amd/mct_ddr3: Work around RDIMM training failure
Under certain conditions, not elucidated in the BKDG,
an extra memclock of CAS write latency is required.
The only reliable way I have found to detect when this
is required is to try training without the delay, and
if DQS position training fails, adding the delay and
retraining.
This is probably related in some form or another to
the badly broken DQS Write Early algorithm given
in the BKDG.
Change-Id: Idfaca1b3da3f45793d210980e952ccdfc9ba1410
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13531
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c index bcf603139e..d8da16b4fe 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c @@ -721,6 +721,7 @@ static u32 mct_MR2(struct MCTStatStruc *pMCTstat, /* Obtain Tcwl, adjust, and set CWL with the adjusted value */ dword = Get_NB32_DCT(dev, dct, 0x20c) & 0x1f; + dword -= pDCTstat->tcwl_delay[dct]; ret |= ((dword - 5) << 3); /* Obtain and set RttWr */ |