amd/amdmct/mct_ddr3: Use training values from previous boot if possible

DRAM training accounts for most of the romstage startup time, yet
if the hardware configuration has not changed from the previous boot
the previously discovered training values are still valid.  Use them
if the DIMM configuration has not changed since the last boot.

The SPD values of all installed DIMMs are hashed and stored in the S3
resume data area of the main system Flash device.  If a DIMM is changed
the hash will almost certainly change as well, forcing retraining on next
boot.

Change-Id: I37ed277b16476d38e4af76c6ae827a575c6b017d
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11976
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

1 files changed, 6 insertions, 0 deletions

diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
index e6b427ed7b..1ac7bbfe62 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
@@ -321,6 +321,10 @@ struct MCTStatStruc {
 struct amd_spd_node_data {
 	uint8_t spd_bytes[MAX_DIMMS_SUPPORTED][256];	/* [DIMM][byte] */
 	uint8_t spd_address[MAX_DIMMS_SUPPORTED];	/* [DIMM] */
+	uint64_t spd_hash[MAX_DIMMS_SUPPORTED];		/* [DIMM] */
+	uint64_t nvram_spd_hash[MAX_DIMMS_SUPPORTED];	/* [DIMM] */
+	uint8_t nvram_spd_match;
+	uint8_t nvram_memclk[2];			/* [channel] */
 } __attribute__((packed));
 
 struct DCTStatStruc {		/* A per Node structure*/
@@ -780,6 +784,8 @@ struct amd_s3_persistent_mct_channel_data {
 
 struct amd_s3_persistent_node_data {
 	uint32_t node_present;
+	uint64_t spd_hash[MAX_DIMMS_SUPPORTED];
+	uint8_t memclk[2];
 	struct amd_s3_persistent_mct_channel_data channel[2];
 } __attribute__((packed));