diff options
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2016-01-30 23:34:51 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-02-05 22:26:31 +0100 |
| commit | 31682364ba062fb3cbf4ff3b0ad7cbdb7b5daae1 (patch) | |
| tree | 0824c0e09657c7fbbdc71c83e9bba0969826f7a9 /src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | |
| parent | 606b6ec686e07930008c5c1710efaaf3d097f465 (diff) | |
nb/amd/mct_ddr3: Work around RDIMM training failure
Under certain conditions, not elucidated in the BKDG,
an extra memclock of CAS write latency is required.
The only reliable way I have found to detect when this
is required is to try training without the delay, and
if DQS position training fails, adding the delay and
retraining.
This is probably related in some form or another to
the badly broken DQS Write Early algorithm given
in the BKDG.
Change-Id: Idfaca1b3da3f45793d210980e952ccdfc9ba1410
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13531
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mct_d.h')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index f953919052..91843d05be 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -597,6 +597,7 @@ struct DCTStatStruc { /* A per Node structure*/ u8 DqsRcvEnGrossMin; u8 WrDatGrossMax; u8 WrDatGrossMin; + uint8_t tcwl_delay[2]; u16 RegMan1Present; /* DIMM present bitmap of Register manufacture 1 */ u16 RegMan2Present; /* DIMM present bitmap of Register manufacture 2 */ @@ -829,7 +830,9 @@ struct amd_s3_persistent_data { #define SB_SmallRCVR 13 /* DQS Rcvr En pass window too small (far right of dynamic range)*/ #define SB_NODQSPOS 14 /* No DQS-DQ passing positions*/ #define SB_SMALLDQS 15 /* DQS-DQ passing window too small*/ -#define SB_DCBKScrubDis 16 /* DCache scrub requested but not enabled */ +#define SB_DCBKScrubDis 16 /* DCache scrub requested but not enabled */ +#define SB_RetryConfigTrain 17 /* Retry configuration and training */ +#define SB_FatalError 18 /* Fatal training error detected */ /*=============================================================================== Local Configuration Status (DCTStatStruc.Status[31:0]) |