src: Get rid of unneeded whitespace

Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

6 files changed, 13 insertions, 12 deletions

diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c
index 8bee4344e7..4267e6d07c 100644
--- a/src/northbridge/amd/amdmct/mct/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct/mct_d.c
@@ -3752,10 +3752,11 @@ void mct_SetDramConfigHi_D(struct DCTStatStruc *pDCTstat, u32 dct,
 	 * Solution: From the bug report:
 	 *  1. A software-initiated frequency change should be wrapped into the
 	 *     following sequence :
-	 * 	- a) Disable Compensation (F2[1, 0]9C_x08[30])
-	 * 	b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines
-	 * 	c) Do frequency change
-	 * 	d) Enable Compensation (F2[1, 0]9C_x08[30])
+	 *	a) Disable Compensation (F2[1, 0]9C_x08[30])
+	 *	b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in
+	 *	   all the compensation engines
+	 *	c) Do frequency change
+	 *	d) Enable Compensation (F2[1, 0]9C_x08[30])
 	 *  2. A software-initiated Disable Compensation should always be
 	 *     followed by step b) of the above steps.
 	 * Silicon Status: Fixed In Rev B0
diff --git a/src/northbridge/amd/amdmct/mct/mct_d_gcc.c b/src/northbridge/amd/amdmct/mct/mct_d_gcc.c
index 59618f6cc0..d826fed96d 100644
--- a/src/northbridge/amd/amdmct/mct/mct_d_gcc.c
+++ b/src/northbridge/amd/amdmct/mct/mct_d_gcc.c
@@ -218,7 +218,7 @@ void ReadL18TestPattern(u32 addr_lo)
 	// set fs and use fs prefix to access the mem
 	__asm__ volatile (
 		"outb %%al, $0xed\n\t"			/* _EXECFENCE */
-		"movl %%fs:-128(%%esi), %%eax\n\t" 	//TestAddr cache line
+		"movl %%fs:-128(%%esi), %%eax\n\t"	//TestAddr cache line
 		"movl %%fs:-64(%%esi), %%eax\n\t"	//+1
 		"movl %%fs:(%%esi), %%eax\n\t"		//+2
 		"movl %%fs:64(%%esi), %%eax\n\t"	//+3
diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c
index 71400071cf..9bb87bbb2a 100644
--- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c
@@ -461,7 +461,7 @@ static void TrainDQSPos_D(struct MCTStatStruc *pMCTstat,
 			continue;
 		}
 
-		BanksPresent = 1; 	/* flag for at least one bank is present */
+		BanksPresent = 1;	/* flag for at least one bank is present */
 		TestAddr = mct_GetMCTSysAddr_D(pMCTstat, pDCTstat, pDCTstat->Channel, ChipSel, &valid);
 		if (!valid) {
 			print_debug_dqs("\t\t\t\tAddress not supported on current CS ", TestAddr, 4);
@@ -762,7 +762,7 @@ static u8 CompareDQSTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStatS
 		test_buf += 2;
 	}
 
-	bytelane = 0;  		/* bytelane counter */
+	bytelane = 0;		/* bytelane counter */
 	bitmap = 0xFF;		/* bytelane test bitmap, 1 = pass */
 	for (i = 0; i < (9 * 64 / 4); i++) { /* sizeof testpattern. /4 due to next loop */
 		value = read32_fs(addr_lo);
diff --git a/src/northbridge/amd/amdmct/mct/mctecc_d.c b/src/northbridge/amd/amdmct/mct/mctecc_d.c
index 9b22c84449..18774ebe7a 100644
--- a/src/northbridge/amd/amdmct/mct/mctecc_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctecc_d.c
@@ -96,7 +96,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
 
 	OB_ECCRedir =  mctGet_NVbits(NV_ECCRedir);	/* ECC Redirection */
 
-	OB_ChipKill = mctGet_NVbits(NV_ChipKill); 	/* ECC Chip-kill mode */
+	OB_ChipKill = mctGet_NVbits(NV_ChipKill);	/* ECC Chip-kill mode */
 
 	OF_ScrubCTL = 0;		/* Scrub CTL for Dcache, L2, and dram */
 	nvbits = mctGet_NVbits(NV_DCBKScrub);
diff --git a/src/northbridge/amd/amdmct/mct/mctmtr_d.c b/src/northbridge/amd/amdmct/mct/mctmtr_d.c
index deb0f8a2e5..1e47ab4c39 100644
--- a/src/northbridge/amd/amdmct/mct/mctmtr_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctmtr_d.c
@@ -36,11 +36,11 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat,
 	/* Set temporary top of memory from Node structure data.
 	 * Adjust temp top of memory down to accommodate 32-bit IO space.
 	 * Bottom40bIO = top of memory, right justified 8 bits
-	 * 	(defines dram versus IO space type)
+	 *	(defines dram versus IO space type)
 	 * Bottom32bIO = sub 4GB top of memory, right justified 8 bits
-	 * 	(defines dram versus IO space type)
+	 *	(defines dram versus IO space type)
 	 * Cache32bTOP = sub 4GB top of WB cacheable memory,
-	 * 	right justified 8 bits
+	 *	right justified 8 bits
 	 */
 
 	val = mctGet_NVbits(NV_BottomIO);
diff --git a/src/northbridge/amd/amdmct/mct/mctsrc.c b/src/northbridge/amd/amdmct/mct/mctsrc.c
index 60857f4052..a29f8eb42e 100644
--- a/src/northbridge/amd/amdmct/mct/mctsrc.c
+++ b/src/northbridge/amd/amdmct/mct/mctsrc.c
@@ -450,7 +450,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat,
 	}
 	if (!_SSE2) {
 		cr4 = read_cr4();
-		cr4 &= ~(1<<9); 	/* restore cr4.OSFXSR */
+		cr4 &= ~(1<<9);		/* restore cr4.OSFXSR */
 		write_cr4(cr4);
 	}