diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-10-23 17:10:27 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-10-30 20:18:53 +0000 |
| commit | 8a643703b87630b4346e52cac3d3acdc95ac1c70 (patch) | |
| tree | e7ec84129a9c02940b8fd8bbd778601b15c0956a /src/northbridge/amd/amdmct/mct | |
| parent | 50f2e4ccec9df213e012c7ecddb0a9c644526c8d (diff) | |
{cpu,drivers,nb,sb}/amd: Replace {MSR,MTRR} addresses with macros
Change-Id: I7e8de35dcdad52bb311b34bfa9b272d17ed3186b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29243
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct/mct_d.c | 4 | ||||
| -rw-r--r-- | src/northbridge/amd/amdmct/mct/mctdqs_d.c | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 91103ffb4f..d03ae9ca98 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -3255,7 +3255,7 @@ static void mct_init(struct MCTStatStruc *pMCTstat, pDCTstat->DRPresent = 1; /* enable extend PCI configuration access */ - addr = 0xC001001F; + addr = NB_CFG_MSR; _RDMSR(addr, &lo, &hi); if (hi & (1 << (46-32))) { pDCTstat->Status |= 1 << SB_ExtConfig; @@ -3556,7 +3556,7 @@ static u8 CheckNBCOFEarlyArbEn(struct MCTStatStruc *pMCTstat, */ /* 3*(Fn2xD4[NBFid]+4)/(2^NbDid)/(3+Fn2x94[MemClkFreq]) */ - _RDMSR(0xC0010071, &lo, &hi); + _RDMSR(MSR_COFVID_STS, &lo, &hi); if (lo & (1 << 22)) NbDid |= 1; diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c index 39c11ce7da..5aadcccf56 100644 --- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c @@ -816,7 +816,7 @@ void SetTargetWTIO_D(u32 TestAddr) u32 lo, hi; hi = TestAddr >> 24; lo = TestAddr << 8; - _WRMSR(0xC0010016, lo, hi); /* IORR0 Base */ + _WRMSR(IORR_FIRST, lo, hi); /* IORR0 Base */ hi = 0xFF; lo = 0xFC000800; /* 64MB Mask */ _WRMSR(0xC0010017, lo, hi); /* IORR0 Mask */ |