diff options
| author | Zheng Bao <zheng.bao@amd.com> | 2010-10-09 07:18:50 +0000 |
|---|---|---|
| committer | Zheng Bao <Zheng.Bao@amd.com> | 2010-10-09 07:18:50 +0000 |
| commit | 53b52f356abe8212f8b06b14c3237ca05b71d597 (patch) | |
| tree | 58f9c1787aebe84ad24ead91f4e1c5f53f56c418 /src/northbridge/amd/amdmct/mct | |
| parent | 1dcf66896dc90edee0dd8eda4d99618f1bc1dcb8 (diff) | |
Trivial. Spell checking.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5928 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/amdmct/mct')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct/mctecc_d.c | 2 | ||||
| -rw-r--r-- | src/northbridge/amd/amdmct/mct/mctmtr_d.c | 6 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/northbridge/amd/amdmct/mct/mctecc_d.c b/src/northbridge/amd/amdmct/mct/mctecc_d.c index 167088f200..87ac3acf36 100644 --- a/src/northbridge/amd/amdmct/mct/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct/mctecc_d.c @@ -61,7 +61,7 @@ static u8 isDramECCEn_D(struct DCTStatStruc *pDCTstat); * guarantee that the NB scrubs the entire dram on its node. Do do this, we * simply sample the scrub ADDR once, for an initial value, then we sample and poll until the polled value of scrub ADDR * has wrapped around at least once: Scrub ADDRi+1 < Scrub ADDRi. Since we let all - * Nodes run in parallel, we need to gaurantee that all nodes have wrapped. To do + * Nodes run in parallel, we need to guarantee that all nodes have wrapped. To do * this efficiently, we need only to sample one of the nodes, the node with the * largest ammount of dram populated is the one which will take the longest amount * of time (the scrub rate is set to max, the same rate, on all nodes). So, diff --git a/src/northbridge/amd/amdmct/mct/mctmtr_d.c b/src/northbridge/amd/amdmct/mct/mctmtr_d.c index 64500f0d58..bc8e944328 100644 --- a/src/northbridge/amd/amdmct/mct/mctmtr_d.c +++ b/src/northbridge/amd/amdmct/mct/mctmtr_d.c @@ -38,7 +38,7 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat, u32 lo, hi; /* Set temporary top of memory from Node structure data. - * Adjust temp top of memory down to accomodate 32-bit IO space. + * Adjust temp top of memory down to accommodate 32-bit IO space. * Bottom40bIO=top of memory, right justified 8 bits * (defines dram versus IO space type) * Bottom32bIO=sub 4GB top of memory, right justified 8 bits @@ -151,7 +151,7 @@ static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType) * 2. Each range must be naturally aligned (Base is same as size) * * There are two code paths: the ascending path and descending path - * (analogous to bsf and bsr), where the next limit is a funtion of the + * (analogous to bsf and bsr), where the next limit is a function of the * next set bit in a forward or backward sequence of bits (as a function * of the Limit). We start with the ascending path, to ensure that * regions are naturally aligned, then we switch to the descending path @@ -219,7 +219,7 @@ void UMAMemTyping_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat u32 lo, hi; /*====================================================================== - * Adjust temp top of memory down to accomodate UMA memory start + * Adjust temp top of memory down to accommodate UMA memory start *======================================================================*/ /* Bottom32bIO=sub 4GB top of memory, right justified 8 bits * (defines dram versus IO space type) |