diff options
| author | Marc Jones <marc.jones@se-eng.com> | 2012-02-21 17:06:40 -0700 |
|---|---|---|
| committer | Marc Jones <marcj303@gmail.com> | 2012-03-02 23:35:26 +0100 |
| commit | 067d22340c68d21f0dd5a33cf02701bc54005a0d (patch) | |
| tree | 36c9dab29b3ef4884dcc9b0d356c70714f1036c5 /src/northbridge/amd/amdmct/mct | |
| parent | 07408e687ce440bf665cd6d04d65075b20db0215 (diff) | |
Fix ECC disable option for AMD Fam10 DDR2 and DDR3.
The logic was backwards on the ECC enable/disable option. Also added better
debug output when the debug RAM init feature is enabled.
Change-Id: I60bffb6149d96cac65011247ef51cd06ed2210c6
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/670
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct/mct_d.c | 2 | ||||
| -rw-r--r-- | src/northbridge/amd/amdmct/mct/mctecc_d.c | 18 |
2 files changed, 13 insertions, 7 deletions
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 5abe6d04dd..36b473a55f 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -300,7 +300,7 @@ restartinit: } mct_FinalMCT_D(pMCTstat, (pDCTstatA + 0) ); // Node 0 - print_t("All Done\n"); + print_tx("mctAutoInitMCT_D Done: Global Status: ", pMCTstat->GStatus); return; fatalexit: diff --git a/src/northbridge/amd/amdmct/mct/mctecc_d.c b/src/northbridge/amd/amdmct/mct/mctecc_d.c index 87ac3acf36..58e61ae0ee 100644 --- a/src/northbridge/amd/amdmct/mct/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct/mctecc_d.c @@ -115,7 +115,6 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) AllECC = 1; MemClrECC = 0; - print_t(" ECCInit 0 \n"); for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { struct DCTStatStruc *pDCTstat; pDCTstat = pDCTstatA + Node; @@ -133,7 +132,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) LDramECC = isDramECCEn_D(pDCTstat); if(pDCTstat->ErrCode != SC_RunningOK) { pDCTstat->Status &= ~(1 << SB_ECCDIMMs); - if (OB_NBECC) { + if (!OB_NBECC) { pDCTstat->ErrStatus |= (1 << SB_DramECCDis); } AllECC = 0; @@ -164,15 +163,12 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) } } /* if Node present */ } - print_t(" ECCInit 1 \n"); if(AllECC) pMCTstat->GStatus |= 1<<GSB_ECCDIMMs; else pMCTstat->GStatus &= ~(1<<GSB_ECCDIMMs); - print_t(" ECCInit 2 \n"); - /* Program the Dram BKScrub CTL to the proper (user selected) value.*/ /* Reset MC4_STS. */ for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { @@ -212,12 +208,22 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) } /*Node has Dram */ } /*if Node present */ } - print_t(" ECCInit 3 \n"); if(mctGet_NVbits(NV_SyncOnUnEccEn)) setSyncOnUnEccEn_D(pMCTstat, pDCTstatA); mctHookAfterECC(); + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { + struct DCTStatStruc *pDCTstat; + pDCTstat = pDCTstatA + Node; + if (NodePresent_D(Node)) { + print_tx("ECCInit: Node ", Node); + print_tx("ECCInit: Status ", pDCTstat->Status); + print_tx("ECCInit: ErrStatus ", pDCTstat->ErrStatus); + print_tx("ECCInit: ErrCode ", pDCTstat->ErrCode); + print_t("ECCInit: Done\n"); + } + } return MemClrECC; } |