diff options
| author | Zheng Bao <zheng.bao@amd.com> | 2010-10-09 02:31:10 +0000 |
|---|---|---|
| committer | Zheng Bao <Zheng.Bao@amd.com> | 2010-10-09 02:31:10 +0000 |
| commit | 1dcf66896dc90edee0dd8eda4d99618f1bc1dcb8 (patch) | |
| tree | 28462953cfdfc2428d03b36ab6ba9ed54584cd85 /src/northbridge/amd/amdmct/mct/mctpro_d.c | |
| parent | 713ae2c0906e442bbe9af6d2e3850ca46e5e10b4 (diff) | |
Trivial. Spell checking.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5927 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/amdmct/mct/mctpro_d.c')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct/mctpro_d.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/amd/amdmct/mct/mctpro_d.c b/src/northbridge/amd/amdmct/mct/mctpro_d.c index a2d08d194e..1539a880eb 100644 --- a/src/northbridge/amd/amdmct/mct/mctpro_d.c +++ b/src/northbridge/amd/amdmct/mct/mctpro_d.c @@ -134,7 +134,7 @@ void mct_BeforeDQSTrain_Samp_D(struct MCTStatStruc *pMCTstat, /* Bug#15880: Determine validity of reset settings for DDR PHY timing * regi.. - * Solutiuon: At least, set WrDqs fine delay to be 0 for DDR2 training. + * Solution: At least, set WrDqs fine delay to be 0 for DDR2 training. */ u32 dev; |