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authorMarc Jones (marc.jones <Marc Jones (marc.jones@amd.com)>2008-04-11 03:20:28 +0000
committerMarc Jones <marc.jones@amd.com>2008-04-11 03:20:28 +0000
commite3aeb93a52d03e1b3dfcf30c66956b18f7f600d7 (patch)
tree84f5632e9d913a7c22f2ee3662704883a93fac79 /src/northbridge/amd/amdmct/mct/mctchi_d.c
parent234e87f137faff67c391c4df678a82b763089119 (diff)
Bring Fam10 memory controller init up to date with the latest AMD BKDG
recomendations. Changes include the following: fix > 4GB dqs tests fix channel interleaving ecc memory scrub updates MC tristating updates debug print changes fix memory hoisting across nodes - The DRAM Hole Address Register is set via devx in each node, but the Node number <-> DRAM Base mapping and the Node number <-> DstNode mapping is set in Node 0. The memmap is setup on node0 and copied to the other nodes later. so dev, not devx. The bug was the hole was always being set on the first node. Signed-off-by: Marc Jones (marc.jones@amd.com) Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3232 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/amdmct/mct/mctchi_d.c')
-rw-r--r--src/northbridge/amd/amdmct/mct/mctchi_d.c17
1 files changed, 8 insertions, 9 deletions
diff --git a/src/northbridge/amd/amdmct/mct/mctchi_d.c b/src/northbridge/amd/amdmct/mct/mctchi_d.c
index 425faf7528..ec6aa96c31 100644
--- a/src/northbridge/amd/amdmct/mct/mctchi_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctchi_d.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -41,11 +41,10 @@ void InterleaveChannels_D(struct MCTStatStruc *pMCTstat,
/* call back to wrapper not needed ManualChannelInterleave_D(); */
/* call back - DctSelIntLvAddr = mctGet_NVbits(NV_ChannelIntlv);*/ /* override interleave */
// FIXME: Check for Cx
- DctSelIntLvAddr = 5; /* use default: Enable channel interleave */
- enabled = 1; /* with Hash*: exclusive OR of address bits[20:16, 6]. */
+ DctSelIntLvAddr = mctGet_NVbits(NV_ChannelIntlv); /* typ=5: Hash*: exclusive OR of address bits[20:16, 6]. */
beforeInterleaveChannels_D(pDCTstatA, &enabled);
- if (enabled) {
+ if (DctSelIntLvAddr & 1) {
DctSelIntLvAddr >>= 1;
HoleSize = 0;
if ((pMCTstat->GStatus & (1 << GSB_SoftHole)) ||
@@ -84,7 +83,7 @@ void InterleaveChannels_D(struct MCTStatStruc *pMCTstat,
dct0_size += DramBase;
dct0_size += dct1_size;
if (dct0_size >= HoleBase) /* if DctSelBaseAddr > HoleBase */
- dct0_size += HoleBase;
+ dct0_size += HoleSize;
DctSelBase = dct0_size;
if (dct1_size == 0)
@@ -100,7 +99,7 @@ void InterleaveChannels_D(struct MCTStatStruc *pMCTstat,
val |= DctSelHi;
val |= (DctSelIntLvAddr << 6) & 0xFF;
Set_NB32(pDCTstat->dev_dct, 0x110, val);
- print_tx("InterleaveChannels: DRAM Controller Select Low Register = ", val);
+ print_tx("InterleaveChannels: F2x110 DRAM Controller Select Low Register = ", val);
if (HoleValid) {
tmp = DramBase;
@@ -112,10 +111,10 @@ void InterleaveChannels_D(struct MCTStatStruc *pMCTstat,
}
tmp += HoleSize;
val = Get_NB32(pDCTstat->dev_map, 0xF0); /* DramHoleOffset */
- val &= 0x7F;
- val |= (tmp & 0xFF);
+ val &= 0xFFFF007F;
+ val |= (tmp & ~0xFFFF007F);
Set_NB32(pDCTstat->dev_map, 0xF0, val);
-print_tx("InterleaveChannels:0xF0 = ", val);
+ print_tx("InterleaveChannels: F1xF0 DRAM Hole Address Register = ", val);
}
}