diff options
author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-03-27 22:50:09 -0500 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-01 21:14:30 +0200 |
commit | 620fa5f30fb0c78bb51aef2dae3a5694ac2c3c87 (patch) | |
tree | 0ca715cdf913b34e96c2327c0cd8248ad28e9b1d /src/northbridge/amd/amdmct/mct/mct_d.h | |
parent | d5c82afa37f99a6db8ebb06d0e3c4c0ad4e488db (diff) |
northbridge/amd/amdfam10: Collect DIMM information for ramstage use
1.) Allow MCT information structures to be copied to cbmem.
2.) Retrieve DIMM vendor, model, and serial information.
3.) Allow maximum installable memory to be set via devicetree.
Change-Id: I0aecd2fb69ebad0a784c01d40ce211f6975a3ece
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/9137
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct/mct_d.h')
-rw-r--r-- | src/northbridge/amd/amdmct/mct/mct_d.h | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h index 0c6df6c25e..a1786965d3 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.h +++ b/src/northbridge/amd/amdmct/mct/mct_d.h @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -231,10 +232,17 @@ #define SPD_TRC 41 #define SPD_TRFC 42 +#define SPD_MANID_START 64 +#define SPD_PARTN_START 73 +#define SPD_PARTN_LENGTH 18 +#define SPD_REVNO_START 91 + #define SPD_MANDATEYR 93 /*Module Manufacturing Year (BCD)*/ #define SPD_MANDATEWK 94 /*Module Manufacturing Week (BCD)*/ +#define SPD_SERIAL_START 95 + /*----------------------------- Jedec DDR II related equates -----------------------------*/ @@ -512,6 +520,18 @@ struct DCTStatStruc { /* A per Node structure*/ u32 dev_map; u32 dev_dct; u32 dev_nbmisc; + + uint8_t DimmRows[MAX_DIMMS_SUPPORTED]; + uint8_t DimmCols[MAX_DIMMS_SUPPORTED]; + uint8_t DimmRanks[MAX_DIMMS_SUPPORTED]; + uint8_t DimmBanks[MAX_DIMMS_SUPPORTED]; + uint8_t DimmWidth[MAX_DIMMS_SUPPORTED]; + uint8_t DimmRegistered[MAX_DIMMS_SUPPORTED]; + + uint64_t DimmManufacturerID[MAX_DIMMS_SUPPORTED]; + char DimmPartNumber[MAX_DIMMS_SUPPORTED][SPD_PARTN_LENGTH]; + uint16_t DimmRevisionNumber[MAX_DIMMS_SUPPORTED]; + uint32_t DimmSerialNumber[MAX_DIMMS_SUPPORTED]; } __attribute__((packed)); /*=============================================================================== @@ -666,6 +686,15 @@ struct DCTStatStruc { /* A per Node structure*/ xx0b = disable yy1b = enable with DctSelIntLvAddr set to yyb */ +/*=============================================================================== + CBMEM storage +===============================================================================*/ +struct amdmct_memory_info { + struct MCTStatStruc mct_stat; + struct DCTStatStruc dct_stat[MAX_NODES_SUPPORTED]; + uint16_t ecc_enabled; + uint16_t ecc_scrub_rate; +} __attribute__((packed)); u32 Get_NB32(u32 dev, u32 reg); void Set_NB32(u32 dev, u32 reg, u32 val); |