cpu/amd: Add CC6 support

This patch adds CC6 power save support to the AMD Family 15h
support code.  As CC6 is a complex power saving state that
relies heavily on CPU, northbridge, and southbridge cooperation,
this patch alters significant amounts of code throughout the
tree simultaneously.

Allowing the CPU to enter CC6 allows the second level of turbo
boost to be reached, and also provides significant power savings
when the system is idle due to the complete core shutdown.

Change-Id: I44ce157cda97fb85f3e8f3d7262d4712b5410670
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11979
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

1 files changed, 34 insertions, 32 deletions

diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h
index 42ad32b1e2..d2dfbccfe9 100644
--- a/src/northbridge/amd/amdmct/amddefs.h
+++ b/src/northbridge/amd/amdmct/amddefs.h
@@ -49,32 +49,34 @@
 /*
  * Groups - Create as many as you wish, from the above public values
  */
-#define	AMD_NPT_F2	(AMD_NPT_F2C | AMD_NPT_F2D | AMD_NPT_F2E | AMD_NPT_F2G | AMD_NPT_F2J | AMD_NPT_F2K)
-#define	AMD_NPT_F3	(AMD_NPT_F3L)
-#define	AMD_NPT_Fx	(AMD_NPT_F0 | AMD_NPT_F1 | AMD_NPT_F2 | AMD_NPT_F3)
-#define	AMD_NPT_Gx	(AMD_NPT_G0A | AMD_NPT_G1B)
-#define	AMD_NPT_ALL	(AMD_NPT_Fx | AMD_NPT_Gx)
-#define	AMD_FINEDELAY	(AMD_NPT_F0 | AMD_NPT_F1 | AMD_NPT_F2)
-#define	AMD_GT_F0	(AMD_NPT_ALL AND NOT AMD_NPT_F0)
-#define	AMD_DR_Ax	(AMD_DR_A0A + AMD_DR_A1B + AMD_DR_A2)
-#define	AMD_DR_Bx	(AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2 | AMD_DR_B3 | AMD_DR_BA)
-#define	AMD_DR_LT_B2	(AMD_DR_B0 | AMD_DR_B1 | AMD_DR_BA)
-#define	AMD_DR_LT_B3	(AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2 | AMD_DR_BA)
-#define	AMD_DR_GT_B0	(AMD_DR_ALL & ~(AMD_DR_B0))
-#define	AMD_DR_GT_Bx	(AMD_DR_ALL & ~(AMD_DR_Ax | AMD_DR_Bx))
-#define	AMD_DR_ALL	(AMD_DR_Bx)
-#define	AMD_FAM10_ALL	(AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 | AMD_HY_D1 | AMD_PH_E0)
-#define AMD_FAM10_LT_D  (AMD_FAM10_ALL & ~(AMD_HY_D0))
-#define	AMD_FAM10_GT_B0	(AMD_FAM10_ALL & ~(AMD_DR_B0))
-#define AMD_FAM10_REV_D	(AMD_HY_D0 | AMD_HY_D1)
-#define	AMD_DA_Cx       (AMD_DA_C2 | AMD_DA_C3)
-#define	AMD_DR_Cx       (AMD_RB_C2 | AMD_RB_C3 | AMD_DA_Cx)
-#define	AMD_FAM10_C3       (AMD_RB_C3 | AMD_DA_C3)
-#define	AMD_DR_Dx	(AMD_HY_D0 | AMD_HY_D1)
-#define	AMD_DRBH_Cx	(AMD_DR_Cx | AMD_HY_D0 )
-#define	AMD_DRBA23_RBC2	(AMD_DR_BA | AMD_DR_B2 | AMD_DR_B3 | AMD_RB_C2 )
+#define	AMD_NPT_F2		(AMD_NPT_F2C | AMD_NPT_F2D | AMD_NPT_F2E | AMD_NPT_F2G | AMD_NPT_F2J | AMD_NPT_F2K)
+#define	AMD_NPT_F3		(AMD_NPT_F3L)
+#define	AMD_NPT_Fx		(AMD_NPT_F0 | AMD_NPT_F1 | AMD_NPT_F2 | AMD_NPT_F3)
+#define	AMD_NPT_Gx		(AMD_NPT_G0A | AMD_NPT_G1B)
+#define	AMD_NPT_ALL		(AMD_NPT_Fx | AMD_NPT_Gx)
+#define	AMD_FINEDELAY		(AMD_NPT_F0 | AMD_NPT_F1 | AMD_NPT_F2)
+#define	AMD_GT_F0		(AMD_NPT_ALL AND NOT AMD_NPT_F0)
+#define	AMD_DR_Ax		(AMD_DR_A0A + AMD_DR_A1B + AMD_DR_A2)
+#define	AMD_DR_Bx		(AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2 | AMD_DR_B3 | AMD_DR_BA)
+#define	AMD_DR_Cx		(AMD_RB_C2 | AMD_RB_C3 | AMD_DA_Cx)
+#define	AMD_DR_Dx		(AMD_HY_D0 | AMD_HY_D1)
+#define	AMD_DR_Ex		(AMD_PH_E0)
+#define	AMD_DR_LT_B2		(AMD_DR_B0 | AMD_DR_B1 | AMD_DR_BA)
+#define	AMD_DR_LT_B3		(AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2 | AMD_DR_BA)
+#define	AMD_DR_GT_B0		(AMD_DR_ALL & ~(AMD_DR_B0))
+#define	AMD_DR_GT_Bx		(AMD_DR_ALL & ~(AMD_DR_Ax | AMD_DR_Bx))
+#define	AMD_DR_GT_D0		((AMD_DR_Dx & ~(AMD_HY_D0)) | AMD_DR_Ex)
+#define	AMD_DR_ALL		(AMD_DR_Bx)
+#define	AMD_FAM10_ALL		(AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 | AMD_HY_D1 | AMD_PH_E0)
+#define AMD_FAM10_LT_D  	(AMD_FAM10_ALL & ~(AMD_HY_D0))
+#define	AMD_FAM10_GT_B0		(AMD_FAM10_ALL & ~(AMD_DR_B0))
+#define AMD_FAM10_REV_D		(AMD_HY_D0 | AMD_HY_D1)
+#define	AMD_DA_Cx       	(AMD_DA_C2 | AMD_DA_C3)
+#define	AMD_FAM10_C3		(AMD_RB_C3 | AMD_DA_C3)
+#define	AMD_DRBH_Cx		(AMD_DR_Cx | AMD_HY_D0 )
+#define	AMD_DRBA23_RBC2		(AMD_DR_BA | AMD_DR_B2 | AMD_DR_B3 | AMD_RB_C2 )
 #define	AMD_DR_DAC2_OR_C3	(AMD_DA_C2 | AMD_DA_C3 | AMD_RB_C3)
-#define	AMD_FAM15_ALL	(AMD_OR_B2 | AMD_OR_C0)
+#define	AMD_FAM15_ALL		(AMD_OR_B2 | AMD_OR_C0)
 
 /*
  *  Public Platforms - USE THESE VERSIONS TO MAKE COMPARE WITH CPUPLATFORMTYPE RETURN VALUE
@@ -87,9 +89,9 @@
 #define	AMD_PTYPE_MC	0x020	/* Multi Core (>2) */
 #define	AMD_PTYPE_UMA	0x040	/* UMA required */
 
-	/*
-	 * Groups - Create as many as you wish, from the above public values
-	 */
+/*
+ * Groups - Create as many as you wish, from the above public values
+ */
 #define	AMD_PTYPE_ALL	0xFFFFFFFF	/* A mask for all */
 
 
@@ -98,11 +100,11 @@
  */
 #define HTPHY_LINKTYPE_HT3		0x00000001
 #define HTPHY_LINKTYPE_HT1		0x00000002
-#define HTPHY_LINKTYPE_COHERENT	0x00000004
+#define HTPHY_LINKTYPE_COHERENT		0x00000004
 #define HTPHY_LINKTYPE_NONCOHERENT	0x00000008
 #define HTPHY_LINKTYPE_CONNECTED	(HTPHY_LINKTYPE_COHERENT | HTPHY_LINKTYPE_NONCOHERENT)
 #define HTPHY_LINKTYPE_GANGED		0x00000010
-#define HTPHY_LINKTYPE_UNGANGED	0x00000020
+#define HTPHY_LINKTYPE_UNGANGED		0x00000020
 #define HTPHY_LINKTYPE_ALL		0x7FFFFFFF
 
 
@@ -110,7 +112,7 @@
  * CPU HT PHY REGISTERS, FIELDS, AND MASKS
  */
 #define HTPHY_OFFSET_MASK		0xE00001FF
-#define HTPHY_WRITE_CMD		0x40000000
+#define HTPHY_WRITE_CMD			0x40000000
 #define HTPHY_IS_COMPLETE_MASK		0x80000000
 #define HTPHY_DIRECT_MAP		0x20000000
 #define HTPHY_DIRECT_OFFSET_MASK	0xE000FFFF
@@ -158,4 +160,4 @@
 #define AMD_PKGTYPE_S1gX 2
 #define AMD_PKGTYPE_G34 3
 #define AMD_PKGTYPE_ASB2 4
-#define AMD_PKGTYPE_C32 5
+#define AMD_PKGTYPE_C32 5
\ No newline at end of file