nb/amd/amdk8: Link raminit_f.c

For this debug.c needs to be linked too.

Change-Id: I9cd1ffff2c39021693fe1d5d3f90ec5f70891f57
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19030
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

11 files changed, 99 insertions, 29 deletions

diff --git a/src/northbridge/amd/amdk8/Makefile.inc b/src/northbridge/amd/amdk8/Makefile.inc
index 7497a07437..fb2aca5cc3 100644
--- a/src/northbridge/amd/amdk8/Makefile.inc
+++ b/src/northbridge/amd/amdk8/Makefile.inc
@@ -4,8 +4,11 @@ ramstage-y += northbridge.c
 ramstage-y += misc_control.c
 ramstage-y += get_sblk_pci1234.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
+
+romstage-y += debug.c
 ifeq ($(CONFIG_K8_REV_F_SUPPORT),y)
 romstage-$(CONFIG_HAVE_ACPI_RESUME) += exit_from_self.c
+romstage-y += raminit_f.c
 endif
 
 # Enable this if you want to check the values of the PCI routing registers.
diff --git a/src/northbridge/amd/amdk8/debug.c b/src/northbridge/amd/amdk8/debug.c
index a8431f4df2..e1eade4265 100644
--- a/src/northbridge/amd/amdk8/debug.c
+++ b/src/northbridge/amd/amdk8/debug.c
@@ -3,7 +3,13 @@
  *
  */
 
-static inline void print_debug_addr(const char *str, void *val)
+#include "debug.h"
+#include <console/console.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <delay.h>
+
+void print_debug_addr(const char *str, void *val)
 {
 #if CONFIG_DEBUG_CAR
 	printk(BIOS_DEBUG, "------Address debug: %s%p------\n", str, val);
@@ -11,12 +17,12 @@ static inline void print_debug_addr(const char *str, void *val)
 }
 
 #if 1
-static void print_debug_pci_dev(unsigned dev)
+void print_debug_pci_dev(unsigned dev)
 {
 	printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x", (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7);
 }
 
-static inline void print_pci_devices(void)
+void print_pci_devices(void)
 {
 	pci_devfn_t dev;
 	for (dev = PCI_DEV(0, 0, 0);
@@ -41,7 +47,7 @@ static inline void print_pci_devices(void)
 	}
 }
 
-static void dump_pci_device(unsigned dev)
+void dump_pci_device(unsigned dev)
 {
 	int i;
 	print_debug_pci_dev(dev);
@@ -58,9 +64,7 @@ static void dump_pci_device(unsigned dev)
 }
 
 #if CONFIG_K8_REV_F_SUPPORT
-static uint32_t pci_read_config32_index_wait(pci_devfn_t dev,
-		uint32_t index_reg, uint32_t index);
-static inline void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg)
+void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg)
 {
 	int i;
 	print_debug_pci_dev(dev);
@@ -81,7 +85,7 @@ static inline void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg)
 }
 #endif
 
-static inline void dump_pci_devices(void)
+void dump_pci_devices(void)
 {
 	pci_devfn_t dev;
 	for (dev = PCI_DEV(0, 0, 0);
@@ -106,7 +110,7 @@ static inline void dump_pci_devices(void)
 	}
 }
 
-static inline void dump_pci_devices_on_bus(unsigned busn)
+void dump_pci_devices_on_bus(unsigned busn)
 {
 	pci_devfn_t dev;
 	for (dev = PCI_DEV(busn, 0, 0);
@@ -133,7 +137,7 @@ static inline void dump_pci_devices_on_bus(unsigned busn)
 
 #if CONFIG_DEBUG_SMBUS
 
-static void dump_spd_registers(const struct mem_controller *ctrl)
+void dump_spd_registers(const struct mem_controller *ctrl)
 {
 	int i;
 	printk(BIOS_DEBUG, "\n");
@@ -179,7 +183,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
 		}
 	}
 }
-static void dump_smbus_registers(void)
+void dump_smbus_registers(void)
 {
 	unsigned device;
 	printk(BIOS_DEBUG, "\n");
@@ -205,7 +209,7 @@ static void dump_smbus_registers(void)
 }
 #endif
 
-static inline void dump_io_resources(unsigned port)
+void dump_io_resources(unsigned port)
 {
 
 	int i;
@@ -225,7 +229,7 @@ static inline void dump_io_resources(unsigned port)
 	}
 }
 
-static inline void dump_mem(unsigned start, unsigned end)
+void dump_mem(unsigned start, unsigned end)
 {
 	unsigned i;
 	printk(BIOS_DEBUG, "dump_mem:");
diff --git a/src/northbridge/amd/amdk8/debug.h b/src/northbridge/amd/amdk8/debug.h
new file mode 100644
index 0000000000..06ed51923b
--- /dev/null
+++ b/src/northbridge/amd/amdk8/debug.h
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef AMDK8_DEBUG_H
+#define AMDK8_DEBUG_H
+
+#include <inttypes.h>
+#include <arch/io.h>
+
+void print_debug_addr(const char *str, void *val);
+void print_debug_pci_dev(unsigned int dev);
+void print_pci_devices(void);
+void dump_pci_device(unsigned int dev);
+void dump_pci_device_index_wait(unsigned int dev, uint32_t index_reg);
+uint32_t pci_read_config32_index_wait(pci_devfn_t dev,
+				uint32_t index_reg, uint32_t index);
+void dump_pci_devices(void);
+void dump_pci_devices_on_bus(unsigned int busn);
+void dump_io_resources(unsigned int port);
+void dump_mem(unsigned start, unsigned end);
+
+#endif
diff --git a/src/northbridge/amd/amdk8/f.h b/src/northbridge/amd/amdk8/f.h
index 506a44970c..f3f9c42614 100644
--- a/src/northbridge/amd/amdk8/f.h
+++ b/src/northbridge/amd/amdk8/f.h
@@ -585,5 +585,7 @@ static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo)
 #endif
 
 void dqs_restore_MC_NVRAM(unsigned int dev);
+void train_ram_on_node(unsigned nodeid, unsigned coreid,
+			       struct sys_info *sysinfo, unsigned retcall);
 
 #endif /* AMDK8_F_H */
diff --git a/src/northbridge/amd/amdk8/f_pci.c b/src/northbridge/amd/amdk8/f_pci.c
index 3ea4003294..230333ab4f 100644
--- a/src/northbridge/amd/amdk8/f_pci.c
+++ b/src/northbridge/amd/amdk8/f_pci.c
@@ -1,6 +1,8 @@
 #ifndef AMDK8_F_PCI_C
 #define AMDK8_F_PCI_C
 
+#include "debug.h"
+
 #ifdef UNUSED_CODE
 /* bit [10,8] are dev func, bit[1,0] are dev index */
 static uint32_t pci_read_config32_index(pci_devfn_t dev, uint32_t index_reg,
@@ -24,7 +26,7 @@ static void pci_write_config32_index(pci_devfn_t dev, uint32_t index_reg,
 }
 #endif
 
-static uint32_t pci_read_config32_index_wait(pci_devfn_t dev,
+uint32_t pci_read_config32_index_wait(pci_devfn_t dev,
 		uint32_t index_reg, uint32_t index)
 {
 	uint32_t dword;
diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c
index b10cd0ef43..168f7ce437 100644
--- a/src/northbridge/amd/amdk8/raminit.c
+++ b/src/northbridge/amd/amdk8/raminit.c
@@ -42,9 +42,9 @@ static int controller_present(const struct mem_controller *ctrl)
 }
 
 #if CONFIG_RAMINIT_SYSINFO
-static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo)
+void sdram_set_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo)
 #else
-static void sdram_set_registers(const struct mem_controller *ctrl)
+void sdram_set_registers(const struct mem_controller *ctrl)
 #endif
 {
 	static const unsigned int register_values[] = {
@@ -2167,9 +2167,9 @@ static long spd_set_dram_timing(const struct mem_controller *ctrl, const struct
 }
 
 #if CONFIG_RAMINIT_SYSINFO
-static void sdram_set_spd_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo)
+void sdram_set_spd_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo)
 #else
-static void sdram_set_spd_registers(const struct mem_controller *ctrl)
+void sdram_set_spd_registers(const struct mem_controller *ctrl)
 #endif
 {
 	struct spd_set_memclk_result result;
@@ -2326,9 +2326,9 @@ void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
 #endif
 
 #if CONFIG_RAMINIT_SYSINFO
-static void sdram_enable(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo)
+void sdram_enable(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo)
 #else
-static void sdram_enable(int controllers, const struct mem_controller *ctrl)
+void sdram_enable(int controllers, const struct mem_controller *ctrl)
 #endif
 {
 	int i;
@@ -2466,7 +2466,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 
 }
 
-static void set_sysinfo_in_ram(unsigned val)
+void set_sysinfo_in_ram(unsigned val)
 {
 }
 
diff --git a/src/northbridge/amd/amdk8/raminit.h b/src/northbridge/amd/amdk8/raminit.h
index 95a99b0d7f..0f4636b43e 100644
--- a/src/northbridge/amd/amdk8/raminit.h
+++ b/src/northbridge/amd/amdk8/raminit.h
@@ -1,6 +1,9 @@
 #ifndef RAMINIT_H
 #define RAMINIT_H
 
+#define NODE_ID		0x60
+#define HT_INIT_CONTROL	0x6c
+
 #define NODE_NUMS 8
 
 #define DIMM_SOCKETS 4
@@ -12,15 +15,28 @@ struct mem_controller {
 };
 
 struct sys_info;
+
 void exit_from_self(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo);
 void setup_resource_map(const unsigned int *register_values, int max);
 void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl);
+int spd_read_byte(unsigned device, unsigned address);
+void activate_spd_rom(const struct mem_controller *ctrl);
+void memreset(int controllers, const struct mem_controller *ctrl);
+void set_sysinfo_in_ram(unsigned int val);
 
 #define TIMEOUT_LOOPS 300000
 
 #if defined(__PRE_RAM__) && CONFIG_RAMINIT_SYSINFO
 void sdram_initialize(int controllers, const struct mem_controller *ctrl, void *sysinfo);
+void sdram_enable(int controllers, const struct mem_controller *ctrl,
+		struct sys_info *sysinfo);
+void sdram_set_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo);
+void sdram_set_spd_registers(const struct mem_controller *ctrl,
+			struct sys_info *sysinfo);
 #else
+void sdram_set_registers(const struct mem_controller *ctrl);
+void sdram_set_spd_registers(const struct mem_controller *ctrl);
+void sdram_enable(int controllers, const struct mem_controller *ctrl);
 void sdram_initialize(int controllers, const struct mem_controller *ctrl);
 #endif
 
diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c
index d6632bbef5..a97989687a 100644
--- a/src/northbridge/amd/amdk8/raminit_f.c
+++ b/src/northbridge/amd/amdk8/raminit_f.c
@@ -16,14 +16,20 @@
  * GNU General Public License for more details.
 */
 
+#include <arch/io.h>
+#include <console/console.h>
 #include <cpu/x86/cache.h>
+#include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/tsc.h>
 #include <cpu/amd/mtrr.h>
+#include <pc80/mc146818rtc.h>
 
 #include <lib.h>
 #include <stdlib.h>
+#include <string.h>
 #include <arch/acpi.h>
+#include "amdk8.h"
 #include "raminit.h"
 #include "f.h"
 #include <spd_ddr2.h>
@@ -90,7 +96,7 @@ static int controller_present(const struct mem_controller *ctrl)
 	return pci_read_config32(ctrl->f0, 0) == 0x11001022;
 }
 
-static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo)
+void sdram_set_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo)
 {
 	static const unsigned int register_values[] = {
 
@@ -2791,7 +2797,7 @@ static long spd_set_dram_timing(const struct mem_controller *ctrl,
 	return meminfo->dimm_mask;
 }
 
-static void sdram_set_spd_registers(const struct mem_controller *ctrl,
+void sdram_set_spd_registers(const struct mem_controller *ctrl,
 				     struct sys_info *sysinfo)
 {
 	struct spd_set_memclk_result result;
@@ -2971,7 +2977,7 @@ void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
 }
 #endif
 
-static void sdram_enable(int controllers, const struct mem_controller *ctrl,
+void sdram_enable(int controllers, const struct mem_controller *ctrl,
 			  struct sys_info *sysinfo)
 {
 	int i;
diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c
index 1e99f338c7..c470b25425 100644
--- a/src/northbridge/amd/amdk8/raminit_f_dqs.c
+++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c
@@ -17,6 +17,12 @@
 #include <arch/stages.h>
 #include <cpu/x86/cr.h>
 #include <cpu/x86/mtrr.h>
+#include <arch/early_variables.h>
+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700)
+#include <southbridge/amd/sb700/sb700.h>
+#else /* IS_ENABLED(CONFIG_SOUTHBRIDGE_VIA_K8T890) */
+#include <southbridge/via/k8t890/k8t890.h>
+#endif
 
 //0: mean no debug info
 #define DQS_TRAIN_DEBUG 0
@@ -1769,7 +1775,7 @@ static void wait_till_sysinfo_in_ram(void)
 }
 #endif
 
-static void set_sysinfo_in_ram(unsigned val)
+void set_sysinfo_in_ram(unsigned val)
 {
 #if CONFIG_MEM_TRAIN_SEQ == 1
 	set_htic_bit(0, val, 9);
@@ -2034,7 +2040,7 @@ static void train_ram(unsigned nodeid, struct sys_info *sysinfo, struct sys_info
 
 }
 
-static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall)
+void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall)
 {
 	if (coreid) return; // only do it on core0
 	struct sys_info *sysinfox;
diff --git a/src/northbridge/amd/amdk8/raminit_test.c b/src/northbridge/amd/amdk8/raminit_test.c
index 3d0b0f46bd..a17f197ccc 100644
--- a/src/northbridge/amd/amdk8/raminit_test.c
+++ b/src/northbridge/amd/amdk8/raminit_test.c
@@ -167,7 +167,7 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
 	/* Nothing to do */
 }
 
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
+void activate_spd_rom(const struct mem_controller *ctrl)
 {
 	/* nothing to do */
 }
diff --git a/src/northbridge/amd/amdk8/reset_test.c b/src/northbridge/amd/amdk8/reset_test.c
index d8734a9a72..f998c48b56 100644
--- a/src/northbridge/amd/amdk8/reset_test.c
+++ b/src/northbridge/amd/amdk8/reset_test.c
@@ -1,7 +1,6 @@
 #include <stdint.h>
 #include <cpu/x86/lapic.h>
-#define NODE_ID		0x60
-#define	HT_INIT_CONTROL 0x6c
+#include "raminit.h"
 
 #define HTIC_ColdR_Detect  (1<<4)
 #define HTIC_BIOSR_Detect  (1<<5)