Clean up #ifs

Replace #if CONFIG_FOO==1 with #if CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1[[:space:]]*\$,#if \1," {} +

Replace #if (CONFIG_FOO==1) with #if CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1)[[:space:]]*\$,#if \1," {} +

Replace #if CONFIG_FOO==0 with #if !CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0[[:space:]]*\$,#if \!\1," {} +

Replace #if (CONFIG_FOO==0) with #if !CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0)[[:space:]]*\$,#if \!\1," {} +

(and some manual changes to fix false positives)

Change-Id: Iac6ca7605a5f99885258cf1a9a2473a92de27c42
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1004
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Martin Roth <martin@se-eng.com>

9 files changed, 51 insertions, 51 deletions

diff --git a/src/northbridge/amd/amdk8/amdk8.h b/src/northbridge/amd/amdk8/amdk8.h
index e353edc479..5aa3b31fbf 100644
--- a/src/northbridge/amd/amdk8/amdk8.h
+++ b/src/northbridge/amd/amdk8/amdk8.h
@@ -2,7 +2,7 @@
 
 #define AMDK8_H
 
-#if CONFIG_K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT
         #include "f.h"
 #else
         #include "pre_f.h"
diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c
index a262686f87..636114df15 100644
--- a/src/northbridge/amd/amdk8/coherent_ht.c
+++ b/src/northbridge/amd/amdk8/coherent_ht.c
@@ -160,7 +160,7 @@ static void disable_probes(void)
 #if 0
 static void enable_apic_ext_id(u8 node)
 {
-#if CONFIG_ENABLE_APIC_EXT_ID==1
+#if CONFIG_ENABLE_APIC_EXT_ID
 #warning "FIXME Is the right place to enable apic ext id here?"
 
       u32 val;
@@ -284,8 +284,8 @@ static uint16_t read_freq_cap(device_t dev, uint8_t pos)
 	freq_cap = pci_read_config16(dev, pos);
 	freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */
 
-#if CONFIG_K8_HT_FREQ_1G_SUPPORT == 1
-    #if CONFIG_K8_REV_F_SUPPORT == 0
+#if CONFIG_K8_HT_FREQ_1G_SUPPORT
+    #if !CONFIG_K8_REV_F_SUPPORT
 	if (!is_cpu_pre_e0())
     #endif
 	{
@@ -665,7 +665,7 @@ static void setup_remote_row_indirect_group(const u8 *conn, int num)
 static void setup_uniprocessor(void)
 {
 	print_spew("Enabling UP settings\n");
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 	unsigned tmp = (pci_read_config32(NODE_MC(0), 0xe8) >> 12) & 3;
 	if (tmp>0) return;
 #endif
@@ -1574,7 +1574,7 @@ static void clear_dead_routes(unsigned nodes)
 }
 #endif /* CONFIG_MAX_PHYSICAL_CPUS > 1 */
 
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 static unsigned verify_dualcore(unsigned nodes)
 {
 	unsigned node, totalcpus, tmp;
@@ -1593,10 +1593,10 @@ static unsigned verify_dualcore(unsigned nodes)
 static void coherent_ht_finalize(unsigned nodes)
 {
 	unsigned node;
-#if CONFIG_K8_REV_F_SUPPORT == 0
+#if !CONFIG_K8_REV_F_SUPPORT
 	int rev_a0;
 #endif
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 	unsigned total_cpus;
 
 	if (read_option(multi_core, 0) == 0) { /* multi_core */
@@ -1614,7 +1614,7 @@ static void coherent_ht_finalize(unsigned nodes)
 	 */
 
 	print_spew("coherent_ht_finalize\n");
-#if CONFIG_K8_REV_F_SUPPORT == 0
+#if !CONFIG_K8_REV_F_SUPPORT
 	rev_a0 = is_cpu_rev_a0();
 #endif
 	for (node = 0; node < nodes; node++) {
@@ -1625,7 +1625,7 @@ static void coherent_ht_finalize(unsigned nodes)
 		/* Set the Total CPU and Node count in the system */
 		val = pci_read_config32(dev, 0x60);
 		val &= (~0x000F0070);
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 		val |= ((total_cpus-1)<<16)|((nodes-1)<<4);
 #else
 		val |= ((nodes-1)<<16)|((nodes-1)<<4);
@@ -1645,7 +1645,7 @@ static void coherent_ht_finalize(unsigned nodes)
 			(3 << HTTC_HI_PRI_BYP_CNT_SHIFT);
 		pci_write_config32(dev, HT_TRANSACTION_CONTROL, val);
 
-#if CONFIG_K8_REV_F_SUPPORT == 0
+#if !CONFIG_K8_REV_F_SUPPORT
 		if (rev_a0) {
 			pci_write_config32(dev, 0x94, 0);
 			pci_write_config32(dev, 0xb4, 0);
@@ -1665,7 +1665,7 @@ static int apply_cpu_errata_fixes(unsigned nodes)
 		device_t dev;
 		uint32_t cmd;
 		dev = NODE_MC(node);
-#if CONFIG_K8_REV_F_SUPPORT == 0
+#if !CONFIG_K8_REV_F_SUPPORT
 		if (is_cpu_pre_c0()) {
 
 			/* Errata 66
@@ -1710,7 +1710,7 @@ static int apply_cpu_errata_fixes(unsigned nodes)
 #endif
 
 
-#if CONFIG_K8_REV_F_SUPPORT == 0
+#if !CONFIG_K8_REV_F_SUPPORT
 		/* I can't touch this msr on early buggy cpus, and cannot apply either 169 or 131 */
 		if (!is_cpu_pre_b3())
 #endif
diff --git a/src/northbridge/amd/amdk8/debug.c b/src/northbridge/amd/amdk8/debug.c
index fd9fe6063e..4f9d8cafa9 100644
--- a/src/northbridge/amd/amdk8/debug.c
+++ b/src/northbridge/amd/amdk8/debug.c
@@ -57,7 +57,7 @@ static void dump_pci_device(unsigned dev)
 	print_debug("\n");
 }
 
-#if CONFIG_K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT
 static uint32_t pci_read_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index);
 static inline void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg)
 {
diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c
index f57eb5bf37..ee1945a123 100644
--- a/src/northbridge/amd/amdk8/incoherent_ht.c
+++ b/src/northbridge/amd/amdk8/incoherent_ht.c
@@ -67,7 +67,7 @@ static void ht_collapse_previous_enumeration(uint8_t bus, unsigned offset_unitid
 	device_t dev;
 
 	//actually, only for one HT device HT chain, and unitid is 0
-#if CONFIG_HT_CHAIN_UNITID_BASE == 0
+#if !CONFIG_HT_CHAIN_UNITID_BASE
 	if(offset_unitid) {
 		return;
 	}
@@ -136,8 +136,8 @@ static uint16_t ht_read_freq_cap(device_t dev, uint8_t pos)
 
 	/* AMD K8 Unsupported 1Ghz? */
 	if (id == (PCI_VENDOR_ID_AMD | (0x1100 << 16))) {
-	#if CONFIG_K8_HT_FREQ_1G_SUPPORT == 1
-		#if CONFIG_K8_REV_F_SUPPORT == 0
+	#if CONFIG_K8_HT_FREQ_1G_SUPPORT
+		#if !CONFIG_K8_REV_F_SUPPORT
 		if (is_cpu_pre_e0()) {  // only E0 later support 1GHz
 			freq_cap &= ~(1 << HT_FREQ_1000Mhz);
 		}
@@ -149,7 +149,7 @@ static uint16_t ht_read_freq_cap(device_t dev, uint8_t pos)
 
 	printk(BIOS_SPEW, "pos=0x%x, filtered freq_cap=0x%x\n", pos, freq_cap);
 
-#if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M890 == 1
+#if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M890
 	freq_cap &= 0x3f;
 	printk(BIOS_INFO, "Limiting HT to 800/600/400/200 MHz until K8M890 HT1000 is fixed.\n");
 #endif
@@ -539,7 +539,7 @@ static int optimize_link_read_pointers_chain(uint8_t ht_c_num)
 		unsigned devn = 1;
 
 	#if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20))
-		#if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
+		#if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
 		if(i==0) // to check if it is sb ht chain
 		#endif
 			devn = CONFIG_HT_CHAIN_UNITID_BASE;
@@ -671,7 +671,7 @@ static int ht_setup_chains(uint8_t ht_c_num)
 
 
 	#if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20))
-		#if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
+		#if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
 		if(i==0) // to check if it is sb ht chain
 		#endif
 			offset_unitid = 1;
diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c
index 7ba2b90406..cc69883007 100644
--- a/src/northbridge/amd/amdk8/misc_control.c
+++ b/src/northbridge/amd/amdk8/misc_control.c
@@ -124,7 +124,7 @@ static void misc_control_init(struct device *dev)
 	cmd = pci_read_config32(dev, 0x44);
 	cmd |= (1<<6) | (1<<25);
 	pci_write_config32(dev, 0x44, cmd );
-#if CONFIG_K8_REV_F_SUPPORT == 0
+#if !CONFIG_K8_REV_F_SUPPORT
 	if (is_cpu_pre_c0()) {
 
 		/* Errata 58
diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c
index 90b4ebf51d..5eeeda21a4 100644
--- a/src/northbridge/amd/amdk8/northbridge.c
+++ b/src/northbridge/amd/amdk8/northbridge.c
@@ -20,7 +20,7 @@
 #include <cpu/x86/lapic.h>
 
 #include <cpu/amd/multicore.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 #include <pc80/mc146818rtc.h>
 #endif
 
@@ -256,7 +256,7 @@ static unsigned amdk8_scan_chains(device_t dev, unsigned max)
 #endif
 		offset_unitid = 0;
 		#if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20))
-			#if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
+			#if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
 			if((nodeid == 0) && (sblink == link->link_num))
 			#endif
 				offset_unitid = 1;
@@ -494,7 +494,7 @@ static void amdk8_create_vga_resource(device_t dev, unsigned nodeid)
 	 * we only deal with the 'first' vga card */
 	for (link = dev->link_list; link; link = link->next) {
 		if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
-#if CONFIG_MULTIPLE_VGA_ADAPTERS == 1
+#if CONFIG_MULTIPLE_VGA_ADAPTERS
 			extern device_t vga_pri; // the primary vga device, defined in device.c
 			printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d link bus range [%d,%d]\n", vga_pri->bus->secondary,
 				link->secondary,link->subordinate);
@@ -635,7 +635,7 @@ static void amdk8_domain_read_resources(device_t dev)
 
 	pci_domain_read_resources(dev);
 
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
+#if CONFIG_PCI_64BIT_PREF_MEM
 	/* Initialize the system wide prefetchable memory resources constraints */
 	resource = new_resource(dev, 2);
 	resource->limit = 0xfcffffffffULL;
@@ -818,11 +818,11 @@ static u32 hoist_memory(unsigned long hole_startk, int node_id)
 }
 #endif
 
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
 #include <cbmem.h>
 #endif
 
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
 extern uint64_t uma_memory_base, uma_memory_size;
 
 static void add_uma_resource(struct device *dev, int index)
@@ -840,7 +840,7 @@ static void add_uma_resource(struct device *dev, int index)
 
 static void amdk8_domain_set_resources(device_t dev)
 {
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
+#if CONFIG_PCI_64BIT_PREF_MEM
 	struct resource *io, *mem1, *mem2;
 	struct resource *res;
 #endif
@@ -857,7 +857,7 @@ static void amdk8_domain_set_resources(device_t dev)
 	io = find_resource(dev, 0);
 	io->base = DEVICE_IO_START;
 #endif
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
+#if CONFIG_PCI_64BIT_PREF_MEM
 	/* Now reallocate the pci resources memory with the
 	 * highest addresses I can manage.
 	 */
@@ -927,7 +927,7 @@ static void amdk8_domain_set_resources(device_t dev)
 	 * if mmio_basek is bigger that hole_basek and will use hole_basek as mmio_basek and we don't need to reset hole.
 	 * otherwise We reset the hole to the mmio_basek
 	 */
-	#if CONFIG_K8_REV_F_SUPPORT == 0
+	#if !CONFIG_K8_REV_F_SUPPORT
 		if (!is_cpu_pre_e0()) {
 	#endif
 
@@ -947,7 +947,7 @@ static void amdk8_domain_set_resources(device_t dev)
 				disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id);
 			}
 
-		#if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1
+		#if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
 			//We need to double check if the mmio_basek is valid for hole setting, if it is equal to basek, we need to decrease it some
 			u32 basek_pri;
 			for (i = 0; i < fx_devs; i++) {
@@ -968,7 +968,7 @@ static void amdk8_domain_set_resources(device_t dev)
 		#endif
 		}
 
-#if CONFIG_K8_REV_F_SUPPORT == 0
+#if !CONFIG_K8_REV_F_SUPPORT
 	} // is_cpu_pre_e0
 #endif
 
@@ -997,7 +997,7 @@ static void amdk8_domain_set_resources(device_t dev)
 		}
 
 
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
 		printk(BIOS_DEBUG, "node %d : uma_memory_base/1024=0x%08llx, mmio_basek=0x%08lx, basek=0x%08x, limitk=0x%08x\n", i, uma_memory_base >> 10, mmio_basek, basek, limitk);
 		if ((uma_memory_base >> 10) < mmio_basek)
 			printk(BIOS_ALERT, "node %d: UMA memory starts below mmio_basek\n", i);
@@ -1014,10 +1014,10 @@ static void amdk8_domain_set_resources(device_t dev)
 					ram_resource(dev, (idx | i), basek, pre_sizek);
 					idx += 0x10;
 					sizek -= pre_sizek;
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
 					if (high_tables_base==0) {
 					/* Leave some space for ACPI, PIRQ and MP tables */
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
 						high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
 #else
 						high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE;
@@ -1030,7 +1030,7 @@ static void amdk8_domain_set_resources(device_t dev)
 				}
 				#if CONFIG_HW_MEM_HOLE_SIZEK != 0
 				if(reset_memhole)
-					#if CONFIG_K8_REV_F_SUPPORT == 0
+					#if !CONFIG_K8_REV_F_SUPPORT
 					if(!is_cpu_pre_e0() )
 					#endif
 		       				 sizek += hoist_memory(mmio_basek,i);
@@ -1049,7 +1049,7 @@ static void amdk8_domain_set_resources(device_t dev)
 		/* If sizek == 0, it was split at mmio_basek without a hole.
 		 * Don't create an empty ram_resource.
 		 */
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
 		/* Deduct uma memory before reporting because
 		 * this is what the mtrr code expects */
 		sizek -= uma_memory_size / 1024;
@@ -1057,12 +1057,12 @@ static void amdk8_domain_set_resources(device_t dev)
 		if (sizek)
 			ram_resource(dev, (idx | i), basek, sizek);
 		idx += 0x10;
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
 		printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n",
 			     i, mmio_basek, basek, limitk);
 		if (high_tables_base==0) {
 		/* Leave some space for ACPI, PIRQ and MP tables */
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
 			high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
 #else
 			high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE;
@@ -1072,7 +1072,7 @@ static void amdk8_domain_set_resources(device_t dev)
 #endif
 	}
 
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
 	add_uma_resource(dev, 7);
 #endif
 	assign_resources(dev->link_list);
@@ -1179,7 +1179,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
 	sysconf.apicid_offset = bsp_apicid;
 
 	disable_siblings = !CONFIG_LOGICAL_CPUS;
-#if CONFIG_LOGICAL_CPUS == 1
+#if CONFIG_LOGICAL_CPUS
 	get_option(&disable_siblings, "multi_core");
 #endif
 
@@ -1248,7 +1248,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
 				// That is the typical case
 
 				if(j == 0 ){
-				       #if CONFIG_K8_REV_F_SUPPORT == 0
+				       #if !CONFIG_K8_REV_F_SUPPORT
 		 		       	e0_later_single_core = is_e0_later_in_bsp(i);  // single core
 				       #else
 				       	e0_later_single_core = is_cpu_f0_in_bsp(i);  // We can read cpuid(1) from Func3
diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c
index 9cb7c60004..7db338b42a 100644
--- a/src/northbridge/amd/amdk8/raminit.c
+++ b/src/northbridge/amd/amdk8/raminit.c
@@ -2289,7 +2289,7 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
 	hole_startk = 4*1024*1024 - CONFIG_HW_MEM_HOLE_SIZEK;
 
 	printk(BIOS_SPEW, "Handling memory hole at 0x%08x (default)\n", hole_startk);
-#if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1
+#if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
 	/* We need to double check if hole_startk is valid.
 	 * If it is equal to the dram base address in K (base_k),
 	 * we need to decrease it.
@@ -2348,7 +2348,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 {
 	int i;
 	u32 whatWait = 0;
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
 	int suspend = acpi_is_wakeup_early();
 #else
 	int suspend = 0;
diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c
index 33df485c8c..86c409f949 100644
--- a/src/northbridge/amd/amdk8/raminit_f.c
+++ b/src/northbridge/amd/amdk8/raminit_f.c
@@ -2965,7 +2965,7 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
 	hole_startk = 4*1024*1024 - CONFIG_HW_MEM_HOLE_SIZEK;
 
 	printk_raminit("Handling memory hole at 0x%08x (default)\n", hole_startk);
-#if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1
+#if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
 	/* We need to double check if the hole_startk is valid, if it is equal
 	   to basek, we need to decrease it some */
 	uint32_t basek_pri;
@@ -3009,7 +3009,7 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
 
 }
 #endif
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
 #include "exit_from_self.c"
 #endif
 
@@ -3017,7 +3017,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
 			  struct sys_info *sysinfo)
 {
 	int i;
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
 	int suspend = acpi_is_wakeup_early();
 #else
 	int suspend = 0;
@@ -3190,7 +3190,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
 	}
 
 
-#if CONFIG_MEM_TRAIN_SEQ ==  0
+#if CONFIG_MEM_TRAIN_SEQ == 0
    #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
 	dqs_timing(controllers, ctrl, tsc0, sysinfo);
    #else
diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c
index 8ddd44fadb..fdec120b50 100644
--- a/src/northbridge/amd/amdk8/raminit_f_dqs.c
+++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c
@@ -1826,7 +1826,7 @@ static void set_sysinfo_in_ram(unsigned val)
 	set_htic_bit(0, val, 9);
 }
 
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
 
 #if CONFIG_MEM_TRAIN_SEQ == 0
 static int save_index_to_pos(unsigned int dev, int size, int index, int nvram_pos)
@@ -1981,7 +1981,7 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc
 		if(train_DqsRcvrEn(ctrl+i, 2, sysinfo)) goto out;
 		printk(BIOS_DEBUG, " done\n");
 		sysinfo->mem_trained[i]=1;
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
 		dqs_save_MC_NVRAM((ctrl+i)->f2);
 #endif
 	}
@@ -2103,7 +2103,7 @@ static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sy
 		memcpy(sysinfo, sysinfox, CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 	#endif
 		set_top_mem_ap(sysinfo->tom_k, sysinfo->tom2_k); // keep the ap's tom consistent with bsp's
-	#if CONFIG_AP_CODE_IN_CAR == 0
+	#if !CONFIG_AP_CODE_IN_CAR
 		printk(BIOS_DEBUG, "CODE IN ROM AND RUN ON NODE: %02x\n", nodeid);
 		train_ram(nodeid, sysinfo, sysinfox);
 	#else