diff options
author | Eric Biederman <ebiederm@xmission.com> | 2003-10-11 06:20:25 +0000 |
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committer | Eric Biederman <ebiederm@xmission.com> | 2003-10-11 06:20:25 +0000 |
commit | 83b991afff40e12a8b6756af06a472842edb1a66 (patch) | |
tree | a441ff0d88afcb0a07cf22dc3653db3e07a05c98 /src/northbridge/amd/amdk8/cpu_rev.c | |
parent | 080038bfbd8fdf08bac12476a3789495e6f705ca (diff) |
- O2, enums, and switch statements work in romcc
- Support for compiling romcc on non x86 platforms
- new romc options -msse and -mmmx for specifying extra registers to use
- Bug fixes to device the device disable/enable framework and an amd8111 implementation
- Move the link specification to the chip specification instead of the path
- Allow specifying devices with internal bridges.
- Initial via epia support
- Opteron errata fixes
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1200 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/amdk8/cpu_rev.c')
-rw-r--r-- | src/northbridge/amd/amdk8/cpu_rev.c | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/src/northbridge/amd/amdk8/cpu_rev.c b/src/northbridge/amd/amdk8/cpu_rev.c new file mode 100644 index 0000000000..51f235905e --- /dev/null +++ b/src/northbridge/amd/amdk8/cpu_rev.c @@ -0,0 +1,25 @@ +/* this is a shrunken cpuid. */ + +static unsigned int cpuid(unsigned int op) +{ + unsigned int ret; + unsigned dummy2,dummy3,dummy4; + + asm volatile ( + "cpuid" + : "=a" (ret), "=b" (dummy2), "=c" (dummy3), "=d" (dummy4) + : "a" (op) + ); + + return ret; +} + +static int is_cpu_rev_a0(void) +{ + return (cpuid(1) & 0xffff) == 0x0f10; +} + +static int is_cpu_pre_c0(void) +{ + return (cpuid(1) & 0xffef) < 0x0f48; +} |