diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-10-24 15:55:53 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-08 11:35:26 +0000 |
| commit | a9473ecbb142d07e95b120dbab6e9e50017f1e55 (patch) | |
| tree | eff72fa0a3176aee0b2568b627553788922c7042 /src/northbridge/amd/amdht | |
| parent | f33e835a064d11179c37d2c306ba024aa3a636fd (diff) | |
src: Replace common MSR addresses with macros
Change-Id: I9fba67be12483ea5e12ccd34c648735d409bc8b0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/northbridge/amd/amdht')
| -rw-r--r-- | src/northbridge/amd/amdht/AsPsDefs.h | 9 | ||||
| -rw-r--r-- | src/northbridge/amd/amdht/h3finit.c | 9 |
2 files changed, 3 insertions, 15 deletions
diff --git a/src/northbridge/amd/amdht/AsPsDefs.h b/src/northbridge/amd/amdht/AsPsDefs.h index 7e6a63d857..30f4d759b6 100644 --- a/src/northbridge/amd/amdht/AsPsDefs.h +++ b/src/northbridge/amd/amdht/AsPsDefs.h @@ -18,9 +18,6 @@ #ifndef ASPSDEFS_H #define ASPSDEFS_H -#define APIC_BAR 0x1b /* APIC_BAR register */ -#define APIC_BAR_BP 0x100 /* APIC_BAR BSP bit */ - /* P-state register offset */ #define PS_REG0 0 /* offset for P0 */ #define PS_REG1 1 /* offset for P1 */ @@ -237,7 +234,6 @@ #define DUAL_PLANE_NB_VID_OFF_MASK 0x3e0000/* for CPU rev <= C */ #define DUAL_PLANE_NB_VID_SHIFT 17/* for CPU rev <= C */ - #define NM_PS_REG (is_fam15h()?8:5) /* number of P-state MSR registers */ /* sFidVidInit.outFlags defines */ @@ -259,7 +255,6 @@ #define VID_1_100V 0x12 /* 1.100V */ #define VID_1_175V 0x1E /* 1.175V */ - /* Nb Fid Code */ #define NB_FID_800M 0x00 /* 800MHz */ @@ -268,13 +263,9 @@ #define NB_DID_1 1 /* GH Logical ID */ - #define GH_REV_A2 0x4 /* GH Rev A2 logical ID, Upper half */ - -#define TSC_MSR 0x10 #define TSC_FREQ_SEL_SHIFT 24 - #define TSC_FREQ_SEL_MASK (1 << TSC_FREQ_SEL_SHIFT) #define WAIT_PSTATE_TIMEOUT 80000000 /* 0.1 s , unit : 1.25 ns */ diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c index 1e2d1a004f..8a85734ea9 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -29,6 +29,7 @@ #include <device/pci.h> #include <console/console.h> +#include <cpu/x86/lapic_def.h> #include <cpu/amd/msr.h> #include <device/pci_def.h> #include <device/pci_ids.h> @@ -42,10 +43,6 @@ *---------------------------------------------------------------------------- */ -/* APIC defines from amdgesa.inc, which can't be included in to c code. */ -#define APIC_Base_BSP 8 -#define APIC_Base 0x1b - #define NVRAM_LIMIT_HT_SPEED_200 0x12 #define NVRAM_LIMIT_HT_SPEED_300 0x11 #define NVRAM_LIMIT_HT_SPEED_400 0x10 @@ -1831,9 +1828,9 @@ static BOOL isSanityCheckOk(void) { uint64 qValue; - AmdMSRRead(APIC_Base, &qValue); + AmdMSRRead(LAPIC_BASE_MSR, &qValue); - return ((qValue.lo & ((u32)1 << APIC_Base_BSP)) != 0); + return ((qValue.lo & LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR) != 0); } /*************************************************************************** |