Fix all warnings in the tree

(does not fix the cmos.layout race yet)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5660 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

5 files changed, 29 insertions, 11 deletions

diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h
index 472e55594f..80b956ac07 100644
--- a/src/northbridge/amd/amdfam10/amdfam10.h
+++ b/src/northbridge/amd/amdfam10/amdfam10.h
@@ -1179,6 +1179,14 @@ void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32
 		offset_pci_dev, u32 offset_io_base);
 
 void setup_resource_map_x(const u32 *register_values, u32 max);
+
+/* reset_test.c */
+u32 cpu_init_detected(u8 nodeid);
+u32 bios_reset_detected(void);
+u32 cold_reset_detected(void);
+u32 other_reset_detected(void);
+u32 get_sblk(void);
+u8 get_sbbusn(u8 sblk);
 #endif
 
 #endif /* AMDFAM10_H */
diff --git a/src/northbridge/amd/amdfam10/amdfam10_conf.c b/src/northbridge/amd/amdfam10/amdfam10_conf.c
index 4ce3e9a471..adfff0f6e3 100644
--- a/src/northbridge/amd/amdfam10/amdfam10_conf.c
+++ b/src/northbridge/amd/amdfam10/amdfam10_conf.c
@@ -61,6 +61,7 @@ static struct dram_base_mask_t get_dram_base_mask(u32 nodeid)
 	return d;
 }
 
+#if CONFIG_AMDMCT == 0
 static void set_dram_base_mask(u32 nodeid, struct dram_base_mask_t d, u32 nodes)
 {
 	u32 i;
@@ -117,8 +118,9 @@ static void set_dram_base_mask(u32 nodeid, struct dram_base_mask_t d, u32 nodes)
 	pci_write_config32(dev, 0x124, d.mask>>8);
 
 }
+#endif
 
-
+#if CONFIG_AMDMCT == 0
 static void set_DctSelBaseAddr(u32 i, u32 sel_m)
 {
 	device_t dev;
@@ -152,7 +154,6 @@ static u32 get_DctSelBaseAddr(u32 i)
 	return sel_m;
 }
 
-#if CONFIG_AMDMCT == 0
 #ifdef UNUSED_CODE
 static void set_DctSelHiEn(u32 i, u32 val)
 {
@@ -234,6 +235,7 @@ static u32 get_one_DCT(struct mem_info *meminfo)
 
 	return one_DCT;
 }
+
 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
 // See that other copy in northbridge.c
 static u32 hoist_memory(u32 hole_startk, u32 i, u32 one_DCT, u32 nodes)
@@ -574,7 +576,7 @@ static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
 }
 #endif
 
-
+#ifdef UNUSED_CODE
 static void re_set_all_config_map_reg(u32 nodes, u32 segbit,
 					sys_info_conf_t *sysinfo)
 {
@@ -616,7 +618,7 @@ static void re_set_all_config_map_reg(u32 nodes, u32 segbit,
 	}
 
 }
-
+#endif
 
 static u32 get_ht_c_index(u32 nodeid, u32 linkn, sys_info_conf_t *sysinfo)
 {
@@ -660,7 +662,7 @@ static void store_ht_c_conf_bus(u32 nodeid, u32 linkn, u32 ht_c_index,
 
 }
 
-
+#ifdef UNUSED_CODE
 static  void set_BusSegmentEn(u32 node, u32 segbit)
 {
 #if CONFIG_PCI_BUS_SEGN_BITS
@@ -679,6 +681,7 @@ static  void set_BusSegmentEn(u32 node, u32 segbit)
 	pci_write_config32(dev, 0x68, dword);
 #endif
 }
+#endif
 
 #if !defined(__PRE_RAM__)
 static u32 get_io_addr_index(u32 nodeid, u32 linkn)
diff --git a/src/northbridge/amd/amdfam10/amdfam10_pci.c b/src/northbridge/amd/amdfam10/amdfam10_pci.c
index bc1bde08d0..d08a9718c7 100644
--- a/src/northbridge/amd/amdfam10/amdfam10_pci.c
+++ b/src/northbridge/amd/amdfam10/amdfam10_pci.c
@@ -32,6 +32,7 @@ static u32 pci_read_config32_index(device_t dev, u32 index_reg, u32 index)
 	return dword;
 }
 
+#ifdef UNUSED_CODE
 static void pci_write_config32_index(device_t dev, u32 index_reg, u32 index, u32 data)
 {
 
@@ -40,6 +41,7 @@ static void pci_write_config32_index(device_t dev, u32 index_reg, u32 index, u32
 	pci_write_config32(dev, index_reg + 0x4, data);
 
 }
+#endif
 
 static u32 pci_read_config32_index_wait(device_t dev, u32 index_reg, u32 index)
 {
@@ -55,6 +57,7 @@ static u32 pci_read_config32_index_wait(device_t dev, u32 index_reg, u32 index)
 	return dword;
 }
 
+#ifdef UNUSED_CODE
 static void pci_write_config32_index_wait(device_t dev, u32 index_reg, u32 index, u32 data)
 {
 
@@ -69,5 +72,6 @@ static void pci_write_config32_index_wait(device_t dev, u32 index_reg, u32 index
 
 }
 #endif
+#endif
 
 
diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c
index fc89ba39c4..f87428ba0c 100644
--- a/src/northbridge/amd/amdfam10/raminit_amdmct.c
+++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c
@@ -17,12 +17,15 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+
+#if (CONFIG_DIMM_SUPPORT & 0x000F)!=0x0005 /* not needed for AMD_FAM10_DDR3 */
 static  void print_tx(const char *strval, u32 val)
 {
 #if CONFIG_DEBUG_RAM_SETUP
 	printk(BIOS_DEBUG, "%s%08x\n", strval, val);
 #endif
 }
+#endif
 
 static  void print_t(const char *strval)
 {
diff --git a/src/northbridge/amd/amdfam10/reset_test.c b/src/northbridge/amd/amdfam10/reset_test.c
index 69869bf48c..21e06d1e2e 100644
--- a/src/northbridge/amd/amdfam10/reset_test.c
+++ b/src/northbridge/amd/amdfam10/reset_test.c
@@ -29,7 +29,7 @@
 
 /* mmconf is not ready */
 /* io_ext is not ready */
-static u32 cpu_init_detected(u8 nodeid)
+u32 cpu_init_detected(u8 nodeid)
 {
 	u32 htic;
 	device_t dev;
@@ -40,7 +40,7 @@ static u32 cpu_init_detected(u8 nodeid)
 	return !!(htic & HTIC_INIT_Detect);
 }
 
-static u32 bios_reset_detected(void)
+u32 bios_reset_detected(void)
 {
 	u32 htic;
 	htic = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), HT_INIT_CONTROL);
@@ -48,7 +48,7 @@ static u32 bios_reset_detected(void)
 	return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect);
 }
 
-static u32 cold_reset_detected(void)
+u32 cold_reset_detected(void)
 {
 	u32 htic;
 	htic = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), HT_INIT_CONTROL);
@@ -56,7 +56,7 @@ static u32 cold_reset_detected(void)
 	return !(htic & HTIC_ColdR_Detect);
 }
 
-static u32 other_reset_detected(void)	// other warm reset not started by BIOS
+u32 other_reset_detected(void)	// other warm reset not started by BIOS
 {
 	u32 htic;
 	htic = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), HT_INIT_CONTROL);
@@ -154,7 +154,7 @@ static u8 node_link_to_bus(u8 node, u8 link) // node are 6 bit, and link three b
 	return 0;
 }
 
-static u32 get_sblk(void)
+u32 get_sblk(void)
 {
 	u32 reg;
 	/* read PCI_DEV(CONFIG_CBB,CONFIG_CDB,0) 0x64 bit [8:9] to find out SbLink m */
@@ -163,7 +163,7 @@ static u32 get_sblk(void)
 }
 
 
-static u8 get_sbbusn(u8 sblk)
+u8 get_sbbusn(u8 sblk)
 {
 	return node_link_to_bus(0, sblk);
 }