diff options
| author | Marc Jones <marc.jones@amd.com> | 2007-12-19 01:32:08 +0000 |
|---|---|---|
| committer | Marc Jones <marc.jones@amd.com> | 2007-12-19 01:32:08 +0000 |
| commit | 8ae8c8822068ef1722c08073ffa4ecc25633cbee (patch) | |
| tree | 8c7bbf2f7b791081e486439a9b7ffb2fd6e649ac /src/northbridge/amd/amdfam10/sspr5.dsl | |
| parent | 2006b38fed2f5f3680de1736f7fc878823f2f93b (diff) | |
Initial AMD Barcelona support for rev Bx.
These are the core files for HyperTransport, DDR2 Memory, and multi-core initialization.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Reviewed-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <myles@pel.cs.byu.edu>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3014 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/amd/amdfam10/sspr5.dsl')
| -rw-r--r-- | src/northbridge/amd/amdfam10/sspr5.dsl | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/src/northbridge/amd/amdfam10/sspr5.dsl b/src/northbridge/amd/amdfam10/sspr5.dsl new file mode 100644 index 0000000000..d63adff512 --- /dev/null +++ b/src/northbridge/amd/amdfam10/sspr5.dsl @@ -0,0 +1,43 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +DefinitionBlock ("SSPR.aml", "SSDT", 1, "AMD-FAM10", "AMD-ACPI", 100925441) +{ + Scope (\_SB) + { + Processor (\_SB.CPAA, 0xbb, 0x120, 6) // CPU0 and 0x01 need to be updated + { + Name(_PCT, Package () + { + ResourceTemplate() {Register (FFixedHW, 0, 0, 0)}, //PERF_CTRL + ResourceTemplate() {Register (FFixedHW, 0, 0, 0)}, //PERF_STATUS + }) + + Name(_PSS, Package() + { + Package(0x06) {0x1111, 0x222222, 0x3333, 0x4444, 0x55, 0x66 }, + Package(0x06) {0x7777, 0x222222, 0x3333, 0x4444, 0x55, 0x66 }, + Package(0x06) {0x8888, 0x222222, 0x3333, 0x4444, 0x55, 0x66 }, + Package(0x06) {0x9999, 0x222222, 0x3333, 0x4444, 0x55, 0x66 }, + Package(0x06) {0xaaaa, 0x222222, 0x3333, 0x4444, 0x55, 0x66 }, + }) + } + + } +} |