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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-12-02 08:56:05 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-12-07 13:00:56 +0100
commite25b5ef39fd10e48e87e0c4770a721a786e36a36 (patch)
tree113c2b4eba9bf7fddd6badbafc3c0f6ac0cef04f /src/northbridge/amd/amdfam10/northbridge.c
parent3d15e10aef5811e8c7146e5defb0e36b848547ed (diff)
MMCONF_SUPPORT: Consolidate resource registration
Change-Id: Id727270bff9e0288747d178c00f3d747fe223b0f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17695 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge/amd/amdfam10/northbridge.c')
-rw-r--r--src/northbridge/amd/amdfam10/northbridge.c9
1 files changed, 1 insertions, 8 deletions
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index cc2e6f923b..43480d2db1 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -741,14 +741,7 @@ static void amdfam10_domain_read_resources(device_t dev)
pci_domain_read_resources(dev);
/* We have MMCONF_SUPPORT, create the resource window. */
- struct resource *res = new_resource(dev, 0xc0010058);
- res->base = CONFIG_MMCONF_BASE_ADDRESS;
- res->size = CONFIG_MMCONF_BUS_NUMBER * 1024 * 1024; /* Each bus needs 1M */
- res->align = log2(res->size);
- res->gran = log2(res->size);
- res->limit = 0xffffffffffffffffULL; /* 64-bit location allowed */
- res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
- IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+ mmconf_resource(dev, 0xc0010058);
/* Reserve lower DRAM region to force PCI MMIO region to correct location above 0xefffffff */
ram_resource(dev, 7, 0, rdmsr(TOP_MEM).lo >> 10);