diff options
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2016-05-07 17:26:40 -0500 |
|---|---|---|
| committer | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2016-05-09 20:44:11 +0200 |
| commit | 84da72c988955c7bdeccf889b1f682582a428752 (patch) | |
| tree | f3bf0fa44f57e04b6301ef3d48029703829c2d50 /src/northbridge/amd/amdfam10/northbridge.c | |
| parent | 251ce85b585b75c90d80b4ae3d0ecd0769afba8a (diff) | |
nb/amd/mct_ddr3: Report correct DIMM size in SMBIOS structure
The existing DIMM size calculation for DDR3 was incorrect. Use
the recommended calculation from the DDR3 SPD specification.
Change-Id: Id6a39e2b38b5d9f483341ebef8f2960ae52bda6c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14739
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/northbridge/amd/amdfam10/northbridge.c')
| -rw-r--r-- | src/northbridge/amd/amdfam10/northbridge.c | 21 |
1 files changed, 18 insertions, 3 deletions
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index da93175b21..19acab61db 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -1199,12 +1199,27 @@ static int amdfam10_get_smbios_data17(int* count, int handle, int parent_handle, * Primary data width * 2^(#rows) * 2^(#cols) * #banks * #ranks */ uint8_t width, rows, cols, banks, ranks; - width = 8; + uint64_t chip_size; + uint32_t chip_width; rows = mem_info->dct_stat[node].DimmRows[slot]; cols = mem_info->dct_stat[node].DimmCols[slot]; ranks = mem_info->dct_stat[node].DimmRanks[slot]; banks = mem_info->dct_stat[node].DimmBanks[slot]; - uint64_t dimm_size_bytes = width * (1ULL << rows) * (1ULL << cols) * banks * ranks; +#if IS_ENABLED(CONFIG_DIMM_DDR3) + chip_size = mem_info->dct_stat[node].DimmChipSize[slot]; + chip_width = mem_info->dct_stat[node].DimmChipWidth[slot]; +#else + chip_size = 0; + chip_width = 0; +#endif + uint64_t dimm_size_bytes; + if (IS_ENABLED(CONFIG_DIMM_DDR3)) { + width = mem_info->dct_stat[node].DimmWidth[slot]; + dimm_size_bytes = ((width / chip_width) * chip_size * ranks) / 8; + } else { + width = 8; + dimm_size_bytes = width * (1ULL << rows) * (1ULL << cols) * banks * ranks; + } memset(t, 0, sizeof(struct smbios_type17)); t->type = SMBIOS_MEMORY_DEVICE; @@ -1213,7 +1228,7 @@ static int amdfam10_get_smbios_data17(int* count, int handle, int parent_handle, t->length = sizeof(struct smbios_type17) - 2; if (dimm_size_bytes > 0x800000000) { t->size = 0x7FFF; - t->extended_size = dimm_size_bytes; + t->extended_size = dimm_size_bytes >> 16; } else { t->size = dimm_size_bytes / (1024*1024); t->size &= (~0x8000); /* size specified in megabytes */ |