northbridge/amd: Add required space before opening parenthesis '('

Change-Id: Ic85f725bbdf72fbac5a4d9482c61343c5eb35e25
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16305
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

1 files changed, 17 insertions, 17 deletions

diff --git a/src/northbridge/amd/amdfam10/acpi.c b/src/northbridge/amd/amdfam10/acpi.c
index d4ad9a409d..51da7d6c88 100644
--- a/src/northbridge/amd/amdfam10/acpi.c
+++ b/src/northbridge/amd/amdfam10/acpi.c
@@ -31,7 +31,7 @@ unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags, u8 l
 	device_t cpu;
 	int cpu_index = 0;
 
-	for(cpu = all_devices; cpu; cpu = cpu->next) {
+	for (cpu = all_devices; cpu; cpu = cpu->next) {
 		if ((cpu->path.type != DEVICE_PATH_APIC) ||
 		   (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) {
 			continue;
@@ -50,7 +50,7 @@ unsigned long acpi_create_srat_lapics(unsigned long current)
 	device_t cpu;
 	int cpu_index = 0;
 
-	for(cpu = all_devices; cpu; cpu = cpu->next) {
+	for (cpu = all_devices; cpu; cpu = cpu->next) {
 		if ((cpu->path.type != DEVICE_PATH_APIC) ||
 		   (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) {
 			continue;
@@ -94,9 +94,9 @@ static void set_srat_mem(void *gp, struct device *dev, struct resource *res)
 	 * next range is from 1M---
 	 * So will cut off before 1M in the mem range
 	 */
-	if((basek+sizek)<1024) return;
+	if ((basek+sizek)<1024) return;
 
-	if(basek<1024) {
+	if (basek<1024) {
 		sizek -= 1024 - basek;
 		basek = 1024;
 	}
@@ -158,9 +158,9 @@ static unsigned long acpi_fill_slit(unsigned long current)
 	*p = (u8) nodes;
 	p += 8;
 
-	for(i=0;i<nodes;i++) {
-		for(j=0;j<nodes; j++) {
-			if(i==j)
+	for (i=0;i<nodes;i++) {
+		for (j=0;j<nodes; j++) {
+			if (i==j)
 				p[i*nodes+j] = 10;
 			else
 				p[i*nodes+j] = 16;
@@ -221,7 +221,7 @@ void northbridge_acpi_write_vars(device_t device)
 
 	acpigen_write_name("BUSN");
 	acpigen_write_package(HC_NUMS);
-	for(i=0; i<HC_NUMS; i++) {
+	for (i=0; i<HC_NUMS; i++) {
 		acpigen_write_dword(sysconf.ht_c_conf_bus[i]);
 	}
 	// minus the opcode
@@ -231,7 +231,7 @@ void northbridge_acpi_write_vars(device_t device)
 
 	acpigen_write_package(HC_NUMS * 4);
 
-	for(i=0;i<(HC_NUMS*2);i++) { // FIXME: change to more chain
+	for (i=0;i<(HC_NUMS*2);i++) { // FIXME: change to more chain
 		acpigen_write_dword(sysconf.conf_mmio_addrx[i]); //base
 		acpigen_write_dword(sysconf.conf_mmio_addr[i]); //mask
 	}
@@ -242,7 +242,7 @@ void northbridge_acpi_write_vars(device_t device)
 
 	acpigen_write_package(HC_NUMS * 2);
 
-	for(i=0;i<HC_NUMS;i++) { // FIXME: change to more chain
+	for (i=0;i<HC_NUMS;i++) { // FIXME: change to more chain
 		acpigen_write_dword(sysconf.conf_io_addrx[i]);
 		acpigen_write_dword(sysconf.conf_io_addr[i]);
 	}
@@ -273,10 +273,10 @@ void northbridge_acpi_write_vars(device_t device)
 
 	acpigen_write_package(HC_POSSIBLE_NUM);
 
-	for(i=0;i<sysconf.hc_possible_num;i++) {
+	for (i=0;i<sysconf.hc_possible_num;i++) {
 		acpigen_write_dword(sysconf.pci1234[i]);
 	}
-	for(i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8
+	for (i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8
 		acpigen_write_dword(0x00000000);
 	}
 	// minus the opcode
@@ -286,10 +286,10 @@ void northbridge_acpi_write_vars(device_t device)
 
 	acpigen_write_package(HC_POSSIBLE_NUM);
 
-	for(i=0;i<sysconf.hc_possible_num;i++) {
+	for (i=0;i<sysconf.hc_possible_num;i++) {
 		acpigen_write_dword(sysconf.hcdn[i]);
 	}
-	for(i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8
+	for (i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8
 		acpigen_write_dword(0x20202020);
 	}
 	// minus the opcode
@@ -299,10 +299,10 @@ void northbridge_acpi_write_vars(device_t device)
 
 	u8 CBST, CBB2, CBS2;
 
-	if(CONFIG_CBB == 0xff) {
+	if (CONFIG_CBB == 0xff) {
 		CBST = (u8) (0x0f);
 	} else {
-		if((sysconf.pci1234[0] >> 12) & 0xff) { //sb chain on  other than bus 0
+		if ((sysconf.pci1234[0] >> 12) & 0xff) { //sb chain on  other than bus 0
 			CBST = (u8) (0x0f);
 		} else {
 			CBST = (u8) (0x00);
@@ -311,7 +311,7 @@ void northbridge_acpi_write_vars(device_t device)
 
 	acpigen_write_name_byte("CBST", CBST);
 
-	if((CONFIG_CBB == 0xff) && (sysconf.nodes>32)) {
+	if ((CONFIG_CBB == 0xff) && (sysconf.nodes>32)) {
 		 CBS2 = 0x0f;
 		 CBB2 = (u8)(CONFIG_CBB-1);
 	} else {