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| author | Kerry She <shekairui@gmail.com> | 2011-08-18 18:03:44 +0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2011-09-07 01:08:57 +0200 |
| commit | feed329a0c006968242aa3065506b5f37f4308d4 (patch) | |
| tree | 0ef0e9e0c112230dd03fe14e199b0be74776b112 /src/northbridge/amd/agesa | |
| parent | 16d3ec6a58b7a7ba52d4d17299b977e5c3e0557f (diff) | |
AMD F14 southbridge update
This change adds the southbridge related code to support
the update of the AMD Family14 cpus to the rec C0 level.
Some of the changes reside in mainboard folders but they
reference changed files in the southbridge folder so they
are included herein.
Change-Id: Ib7786f9f697eaf0bf8abd9140c4dd0c42927ec7e
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Signed-off-by: Kerry She <kerry.she@amd.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/135
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/northbridge/amd/agesa')
| -rw-r--r-- | src/northbridge/amd/agesa/family14/northbridge.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index e38500d56f..80b9ca6853 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -33,6 +33,9 @@ #include "chip.h" #include "northbridge.h" +#if CONFIG_AMD_SB_CIMX +#include <sb_cimx.h> +#endif //#define FX_DEVS NODE_NUMS @@ -747,6 +750,12 @@ printk(BIOS_DEBUG, " adsr - leaving this lovely routine.\n"); static void domain_enable_resources(device_t dev) { u32 val; + +#if CONFIG_AMD_SB_CIMX + sb_After_Pci_Init(); + sb_Mid_Post_Init(); +#endif + /* Must be called after PCI enumeration and resource allocation */ printk(BIOS_DEBUG, "\nFam14h - domain_enable_resources: AmdInitMid.\n"); val = agesawrapper_amdinitmid (); |