From feed329a0c006968242aa3065506b5f37f4308d4 Mon Sep 17 00:00:00 2001 From: Kerry She Date: Thu, 18 Aug 2011 18:03:44 +0800 Subject: AMD F14 southbridge update This change adds the southbridge related code to support the update of the AMD Family14 cpus to the rec C0 level. Some of the changes reside in mainboard folders but they reference changed files in the southbridge folder so they are included herein. Change-Id: Ib7786f9f697eaf0bf8abd9140c4dd0c42927ec7e Signed-off-by: Frank Vibrans Signed-off-by: efdesign98 Signed-off-by: Kerry She Signed-off-by: Kerry She Reviewed-on: http://review.coreboot.org/135 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/northbridge/amd/agesa/family14/northbridge.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'src/northbridge/amd/agesa') diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index e38500d56f..80b9ca6853 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -33,6 +33,9 @@ #include "chip.h" #include "northbridge.h" +#if CONFIG_AMD_SB_CIMX +#include +#endif //#define FX_DEVS NODE_NUMS @@ -747,6 +750,12 @@ printk(BIOS_DEBUG, " adsr - leaving this lovely routine.\n"); static void domain_enable_resources(device_t dev) { u32 val; + +#if CONFIG_AMD_SB_CIMX + sb_After_Pci_Init(); + sb_Mid_Post_Init(); +#endif + /* Must be called after PCI enumeration and resource allocation */ printk(BIOS_DEBUG, "\nFam14h - domain_enable_resources: AmdInitMid.\n"); val = agesawrapper_amdinitmid (); -- cgit v1.2.3