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authorElyes HAOUAS <ehaouas@noos.fr>2018-10-12 10:54:30 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-10-18 12:51:26 +0000
commit400ce55566caa541304b2483e61bcc2df941998c (patch)
tree4e0cbf4aef7fb00a9c40327075ffa9737e56b104 /src/northbridge/amd/agesa/family16kb
parente64a585374de88ea896ed517445a34986aa321b9 (diff)
cpu/amd: Use common AMD's MSR
Phase 1. Due to the size of the effort, this CL is broken into several phases. Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/northbridge/amd/agesa/family16kb')
-rw-r--r--src/northbridge/amd/agesa/family16kb/northbridge.c6
1 files changed, 2 insertions, 4 deletions
diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c
index 6e0eabaa50..a42ee5cd51 100644
--- a/src/northbridge/amd/agesa/family16kb/northbridge.c
+++ b/src/northbridge/amd/agesa/family16kb/northbridge.c
@@ -27,15 +27,13 @@
#include <lib.h>
#include <cpu/cpu.h>
#include <cbmem.h>
-
#include <cpu/x86/lapic.h>
+#include <cpu/amd/msr.h>
#include <cpu/amd/mtrr.h>
-
#include <Porting.h>
#include <AGESA.h>
#include <Options.h>
#include <Topology.h>
-
#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/agesa_helper.h>
@@ -306,7 +304,7 @@ static void read_resources(struct device *dev)
* It is not honored by the coreboot resource allocator if it is in
* the APIC_CLUSTER.
*/
- mmconf_resource(dev, 0xc0010058);
+ mmconf_resource(dev, MMIO_CONF_BASE);
}
static void set_resource(struct device *dev, struct resource *resource, u32 nodeid)