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authorEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-11-20 19:58:09 +1100
committerEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-11-24 05:37:50 +0100
commitae5fd3453a61d95b9f786b4412cb1705563e81cb (patch)
tree17a8701b047d2576cbc2282cf0003cad71c856e8 /src/northbridge/amd/agesa/family16kb/dimmSpd.c
parent9e999d6a14783ae15bf7f6d8843ea667fd8888e7 (diff)
northbridge/amd/agesa/family1{4,5,5tn,6kb}: Reduce differences
Lets cut down on whitespace differences, fix some typos and indents. Also make use of ARRAY_SIZE() macro instead of a local redefinition. Fix NULL pointer checks ordering and not to use zero. Change-Id: I93f344d300c04570d795659d848255cb1832e1d8 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7528 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/northbridge/amd/agesa/family16kb/dimmSpd.c')
-rw-r--r--src/northbridge/amd/agesa/family16kb/dimmSpd.c26
1 files changed, 16 insertions, 10 deletions
diff --git a/src/northbridge/amd/agesa/family16kb/dimmSpd.c b/src/northbridge/amd/agesa/family16kb/dimmSpd.c
index 8991bdb69e..6ffdf5d985 100644
--- a/src/northbridge/amd/agesa/family16kb/dimmSpd.c
+++ b/src/northbridge/amd/agesa/family16kb/dimmSpd.c
@@ -19,6 +19,7 @@
#include <device/pci_def.h>
#include <device/device.h>
+#include <stdlib.h>
/* warning: Porting.h includes an open #pragma pack(1) */
#include "Porting.h"
@@ -26,28 +27,33 @@
#include "amdlib.h"
#include "chip.h"
-#include "northbridge/amd/agesa/dimmSpd.h"
-
-#define DIMENSION(array)(sizeof (array)/ sizeof (array [0]))
+#include <northbridge/amd/agesa/dimmSpd.h>
+/**
+ * Gets the SMBus address for an SPD from the array in devicetree.cb
+ * then read the SPD into the supplied buffer.
+ */
AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info)
{
- int spdAddress;
+ UINT8 spdAddress;
+
ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
- ROMSTAGE_CONST struct northbridge_amd_agesa_family16kb_config *config = dev->chip_info;
+ if (dev == NULL)
+ return AGESA_ERROR;
- if ((dev == 0) || (config == 0))
+ ROMSTAGE_CONST struct northbridge_amd_agesa_family16kb_config *config = dev->chip_info;
+ if (config == NULL)
return AGESA_ERROR;
- if (info->SocketId >= DIMENSION(config->spdAddrLookup ))
+ if (info->SocketId >= ARRAY_SIZE(config->spdAddrLookup))
return AGESA_ERROR;
- if (info->MemChannelId >= DIMENSION(config->spdAddrLookup[0] ))
+ if (info->MemChannelId >= ARRAY_SIZE(config->spdAddrLookup[0]))
return AGESA_ERROR;
- if (info->DimmId >= DIMENSION(config->spdAddrLookup[0][0]))
+ if (info->DimmId >= ARRAY_SIZE(config->spdAddrLookup[0][0]))
return AGESA_ERROR;
spdAddress = config->spdAddrLookup
- [info->SocketId] [info->MemChannelId] [info->DimmId];
+ [info->SocketId][info->MemChannelId][info->DimmId];
if (spdAddress == 0)
return AGESA_ERROR;