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authorKyösti Mälkki <kyosti.malkki@gmail.com>2013-08-12 21:35:20 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2014-11-23 20:36:16 +0100
commitb8ef4c9a840ebf1549694db9967f101ab2211db6 (patch)
tree37ca70d162e9b790384c245f6e47a011e34e7c99 /src/northbridge/amd/agesa/family15tn
parent46249be26753319877d67b2958c5070f179b5937 (diff)
usbdebug: Reduce bus reset delays
According to EHCI specification, host controller software stops the USB Reset condition by writing PORT_RESET=0. Software then poll-waits this bit until controller hardware has completed USB Reset sequence and read returns with PORT_RESET==0. Change-Id: I6033c4d904c2af9eb16f5f3c1eb825776648cc1d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3863 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/northbridge/amd/agesa/family15tn')
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