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authorKyösti Mälkki <kyosti.malkki@gmail.com>2018-05-22 01:15:17 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-01-04 21:22:04 +0000
commit4ad7f5b1a4f81343cee634a3a49145a3ed9855b7 (patch)
tree6d94849295621aa816ac37a48cf8cf94b066bc4f /src/northbridge/amd/agesa/family15tn
parent33ff44c37ccb96c209b002e5430deefc00cc5591 (diff)
AGESA: Use pcidev_on_root()
We have constant CONFIG_CBB==0, replace ill dev_find_slot() with safe pcidev_on_root(); Change-Id: Ieb2030fa3d77a9f49fc5faf12b92b5f00f49d354 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/26482 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/amd/agesa/family15tn')
-rw-r--r--src/northbridge/amd/agesa/family15tn/dimmSpd.c2
-rw-r--r--src/northbridge/amd/agesa/family15tn/northbridge.c12
2 files changed, 7 insertions, 7 deletions
diff --git a/src/northbridge/amd/agesa/family15tn/dimmSpd.c b/src/northbridge/amd/agesa/family15tn/dimmSpd.c
index 528bc4337c..7ca47097b2 100644
--- a/src/northbridge/amd/agesa/family15tn/dimmSpd.c
+++ b/src/northbridge/amd/agesa/family15tn/dimmSpd.c
@@ -32,7 +32,7 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINTN unused2, AGESA_READ_SPD_PAR
{
UINT8 spdAddress;
- DEVTREE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
+ DEVTREE_CONST struct device *dev = pcidev_on_root(0x18, 2);
if (dev == NULL)
return AGESA_ERROR;
diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c
index ae0830c731..f1a2051233 100644
--- a/src/northbridge/amd/agesa/family15tn/northbridge.c
+++ b/src/northbridge/amd/agesa/family15tn/northbridge.c
@@ -99,7 +99,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
static struct device *get_node_pci(u32 nodeid, u32 fn)
{
- return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
+ return pcidev_on_root(CONFIG_CDB + nodeid, fn);
}
static void get_fx_devs(void)
@@ -818,7 +818,7 @@ static void cpu_bus_scan(struct device *dev)
int siblings = 0;
unsigned int family;
- dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0));
+ dev_mc = pcidev_on_root(CONFIG_CDB, 0);
if (!dev_mc) {
printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB);
die("");
@@ -847,7 +847,7 @@ static void cpu_bus_scan(struct device *dev)
pbus = dev_mc->bus;
/* Find the cpu's pci device */
- cdb_dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(devn, 0));
+ cdb_dev = pcidev_on_root(devn, 0);
if (!cdb_dev) {
/* If I am probing things in a weird order
* ensure all of the cpu's pci devices are found.
@@ -857,7 +857,7 @@ static void cpu_bus_scan(struct device *dev)
cdb_dev = pci_probe_dev(NULL, pbus,
PCI_DEVFN(devn, fn));
}
- cdb_dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(devn, 0));
+ cdb_dev = pcidev_on_root(devn, 0);
} else {
/* Ok, We need to set the links for that device.
* otherwise the device under it will not be scanned
@@ -869,11 +869,11 @@ static void cpu_bus_scan(struct device *dev)
family = (family >> 20) & 0xFF;
if (family == 1) { //f10
u32 dword;
- cdb_dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(devn, 3));
+ cdb_dev = pcidev_on_root(devn, 3);
dword = pci_read_config32(cdb_dev, 0xe8);
siblings = ((dword & BIT15) >> 13) | ((dword & (BIT13 | BIT12)) >> 12);
} else if (family == 6) {//f15
- cdb_dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(devn, 5));
+ cdb_dev = pcidev_on_root(devn, 5);
if (cdb_dev && cdb_dev->enabled) {
siblings = pci_read_config32(cdb_dev, 0x84);
siblings &= 0xFF;