diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-10-12 10:54:30 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-18 12:51:26 +0000 |
| commit | 400ce55566caa541304b2483e61bcc2df941998c (patch) | |
| tree | 4e0cbf4aef7fb00a9c40327075ffa9737e56b104 /src/northbridge/amd/agesa/family15tn | |
| parent | e64a585374de88ea896ed517445a34986aa321b9 (diff) | |
cpu/amd: Use common AMD's MSR
Phase 1. Due to the size of the effort, this CL is broken into several
phases.
Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/northbridge/amd/agesa/family15tn')
| -rw-r--r-- | src/northbridge/amd/agesa/family15tn/northbridge.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 76fd747c91..7248eb79a0 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -29,14 +29,12 @@ #include <cpu/cpu.h> #include <cbmem.h> #include <AGESA.h> - #include <cpu/x86/lapic.h> +#include <cpu/amd/msr.h> #include <cpu/amd/mtrr.h> - #include <Porting.h> #include <Options.h> #include <Topology.h> - #include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/agesa_helper.h> @@ -307,7 +305,7 @@ static void nb_read_resources(struct device *dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - mmconf_resource(dev, 0xc0010058); + mmconf_resource(dev, MMIO_CONF_BASE); } static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) |