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authorStefan Reinauer <reinauer@chromium.org>2013-02-12 15:20:54 -0800
committerRonald G. Minnich <rminnich@gmail.com>2013-02-14 07:07:20 +0100
commit0aa37c488bf785466e0db9897805ebf287af48eb (patch)
treebbbdb3fd2cd6e9972d44df79e5c1232ba1928111 /src/northbridge/amd/agesa/family15tn
parent398e84c71a15b7db8c631bb5b17d1a1a60c91128 (diff)
sconfig: rename lapic_cluster -> cpu_cluster
The name lapic_cluster is a bit misleading, since the construct is not local APIC specific by concept. As implementations and hardware change, be more generic about our naming. This will allow us to support non-x86 systems without adding new keywords. Change-Id: Icd7f5fcf6f54d242eabb5e14ee151eec8d6cceb1 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2377 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge/amd/agesa/family15tn')
-rw-r--r--src/northbridge/amd/agesa/family15tn/northbridge.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c
index 41c2d8e506..144dde726f 100644
--- a/src/northbridge/amd/agesa/family15tn/northbridge.c
+++ b/src/northbridge/amd/agesa/family15tn/northbridge.c
@@ -341,7 +341,7 @@ static void nb_read_resources(device_t dev)
/*
* This MMCONF resource must be reserved in the PCI domain.
* It is not honored by the coreboot resource allocator if it is in
- * the APIC_CLUSTER.
+ * the CPU_CLUSTER.
*/
#if CONFIG_MMCONF_SUPPORT
struct resource *resource = new_resource(dev, 0xc0010058);
@@ -1125,7 +1125,7 @@ static void root_complex_enable_dev(struct device *dev)
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN) {
dev->ops = &pci_domain_ops;
- } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
+ } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
dev->ops = &cpu_bus_ops;
}
}