diff options
author | Mike Banon <mikebdp2@gmail.com> | 2020-08-15 10:30:19 +0300 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2020-08-24 09:18:12 +0000 |
commit | 8b7bda40f140e3d849a91660d2c84a4c324c8901 (patch) | |
tree | 7349796f92e0f5864397fc74a79210b8d889e56d /src/northbridge/amd/agesa/family15tn/dimmSpd.c | |
parent | d2a00d7a1c7c93b9f149e1c2c8150c1114d1374d (diff) |
nb/amd/agesa: define DDR3_SPD_SIZE as a common value
Move a size of DDR3 SPD memory (always 256 bytes) to a common define.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I80c89ff6e44526e1d75b0e933b21801ed17c98c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/northbridge/amd/agesa/family15tn/dimmSpd.c')
-rw-r--r-- | src/northbridge/amd/agesa/family15tn/dimmSpd.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/amd/agesa/family15tn/dimmSpd.c b/src/northbridge/amd/agesa/family15tn/dimmSpd.c index 6504d1475d..70a7b92be0 100644 --- a/src/northbridge/amd/agesa/family15tn/dimmSpd.c +++ b/src/northbridge/amd/agesa/family15tn/dimmSpd.c @@ -39,7 +39,7 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINTN unused2, AGESA_READ_SPD_PAR if (spdAddress == 0) return AGESA_ERROR; - int err = hudson_readSpd(spdAddress, (void *) info->Buffer, 256); + int err = hudson_readSpd(spdAddress, (void *) info->Buffer, DDR3_SPD_SIZE); if (err) return AGESA_ERROR; return AGESA_SUCCESS; |