summaryrefslogtreecommitdiff
path: root/src/northbridge/amd/agesa/family15rl/acpi
diff options
context:
space:
mode:
authorEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-11-21 02:45:10 +1100
committerEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-11-27 11:27:45 +0100
commit12bb8f97b6e453ea2cc99607efb443025271f3d8 (patch)
treef9203e21e00bfae508642c99a092d34709e69cc1 /src/northbridge/amd/agesa/family15rl/acpi
parentd305aa6fc4fe1bedf591cae46409016a677c94ef (diff)
northbridge/amd/agesa/family15rl: Provide Richland support
Provide our current development support for Richland. We would however like to see a unification of 'northbridge/amd/agesa' instead of another copy-paste merged. Change-Id: I88005939844d1132cfd3531a9d47389320026814 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7536 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/northbridge/amd/agesa/family15rl/acpi')
-rw-r--r--src/northbridge/amd/agesa/family15rl/acpi/northbridge.asl100
1 files changed, 100 insertions, 0 deletions
diff --git a/src/northbridge/amd/agesa/family15rl/acpi/northbridge.asl b/src/northbridge/amd/agesa/family15rl/acpi/northbridge.asl
new file mode 100644
index 0000000000..28c00029d0
--- /dev/null
+++ b/src/northbridge/amd/agesa/family15rl/acpi/northbridge.asl
@@ -0,0 +1,100 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Note: Only need HID on Primary Bus */
+External (TOM1)
+External (TOM2)
+Name(_HID, EISAID("PNP0A03")) /* PCI Express Root Bridge */
+Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
+
+/* Describe the Northbridge devices */
+
+Method (_BBN, 0, NotSerialized)
+{
+ Return (Zero)
+}
+
+Method (_STA, 0, NotSerialized)
+{
+ Return (0x0B)
+}
+
+Method (_PRT, 0, NotSerialized)
+{
+ If (PMOD)
+ {
+ Return (APR0)
+ }
+
+ Return (PR0)
+}
+
+Device(AMRT) {
+ Name(_ADR, 0x00000000)
+} /* end AMRT */
+
+/* Dev2 is also an external GFX bridge */
+Device(PBR2) {
+ Name(_ADR, 0x00020000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS2) } /* APIC mode */
+ Return (PS2) /* PIC Mode */
+ } /* end _PRT */
+} /* end PBR2 */
+
+/* Dev4 GPP0 Root Port Bridge */
+Device(PBR4) {
+ Name(_ADR, 0x00040000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS4) } /* APIC mode */
+ Return (PS4) /* PIC Mode */
+ } /* end _PRT */
+} /* end PBR4 */
+
+/* Dev5 GPP1 Root Port Bridge */
+Device(PBR5) {
+ Name(_ADR, 0x00050000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS5) } /* APIC mode */
+ Return (PS5) /* PIC Mode */
+ } /* end _PRT */
+} /* end PBR5 */
+
+/* Dev6 GPP2 Root Port Bridge */
+Device(PBR6) {
+ Name(_ADR, 0x00060000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS6) } /* APIC mode */
+ Return (PS6) /* PIC Mode */
+ } /* end _PRT */
+} /* end PBR6 */
+
+/* The onboard EtherNet chip */
+Device(PBR7) {
+ Name(_ADR, 0x00070000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS7) } /* APIC mode */
+ Return (PS7) /* PIC Mode */
+ } /* end _PRT */
+} /* end PBR7 */