diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-11-20 11:03:13 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-12-01 05:49:09 +0100 |
| commit | 59e03342076ea79cb7c0ed2fdbd199947c8c5212 (patch) | |
| tree | ec951913b7ad95c35faced30b4dadc6413619b5d /src/northbridge/amd/agesa/family12 | |
| parent | 7d09cfcf749c1c0fd1c3791585065b39ec1a3433 (diff) | |
AGESA: Switch to MMCONF_SUPPORT_DEFAULT
Vendorcode always does PCI MMCONF access once it is
enabled via MSR.
In coreboot proper, we don't give opportunity to make
pci_read/write calls before PCI MMCONF is enabled via MSR.
This happens early in romstage amd_initmmio() for all cores.
Change-Id: If31bc0a67b480bcc1d955632f413f5cdeec51a54
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17533
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge/amd/agesa/family12')
| -rw-r--r-- | src/northbridge/amd/agesa/family12/Kconfig | 1 | ||||
| -rw-r--r-- | src/northbridge/amd/agesa/family12/northbridge.c | 2 |
2 files changed, 0 insertions, 3 deletions
diff --git a/src/northbridge/amd/agesa/family12/Kconfig b/src/northbridge/amd/agesa/family12/Kconfig index 9d4995440e..f967837b3c 100644 --- a/src/northbridge/amd/agesa/family12/Kconfig +++ b/src/northbridge/amd/agesa/family12/Kconfig @@ -17,7 +17,6 @@ config NORTHBRIDGE_AMD_AGESA_FAMILY12 select HAVE_DEBUG_RAM_SETUP select HAVE_DEBUG_SMBUS select HYPERTRANSPORT_PLUGIN_SUPPORT - select MMCONF_SUPPORT if NORTHBRIDGE_AMD_AGESA_FAMILY12 diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 9b2634cb68..6f2896aa5a 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -649,13 +649,11 @@ static void cpu_bus_read_resources(device_t dev) { printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); -#if CONFIG_MMCONF_SUPPORT struct resource *resource = new_resource(dev, 0xc0010058); resource->base = CONFIG_MMCONF_BASE_ADDRESS; resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256; resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -#endif printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } |