summaryrefslogtreecommitdiff
path: root/src/mainboard
diff options
context:
space:
mode:
authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-10-02 23:29:07 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-10-05 13:21:55 +0000
commitf9891c8b469232cca28f0b12f613274f127748df (patch)
treeb10131ca552bcce69e92490a5f4a76575405387a /src/mainboard
parentad787e18e0ed24495132d0e9e638ed835afad354 (diff)
kontron/986lcd-m,roda/rk886ex: Drop secondary PCI reset
The extra PCI bus RST# and 200ms delay there was workaround for custom add-on hardware. Change-Id: I38c4677cfb41d620498be8e0c257b517995bad5c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/kontron/986lcd-m/romstage.c3
-rw-r--r--src/mainboard/roda/rk886ex/romstage.c3
2 files changed, 0 insertions, 6 deletions
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index c0e6071301..7fa1b4271e 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -245,9 +245,6 @@ void mainboard_romstage_entry(void)
enable_lapic();
- /* Force PCIRST# to conventional PCI slot and Firewire. */
- ich7_p2p_secondary_reset();
-
ich7_enable_lpc();
early_superio_config_w83627thg();
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index 7949b697b7..f550632d30 100644
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -208,9 +208,6 @@ void mainboard_romstage_entry(void)
enable_lapic();
- /* Force PCIRST# to cardbus add-on. */
- ich7_p2p_secondary_reset();
-
ich7_enable_lpc();
early_superio_config();