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authorSubrata Banik <subratabanik@google.com>2023-07-25 16:14:08 +0000
committerFelix Held <felix-coreboot@felixheld.de>2023-07-31 14:04:04 +0000
commitedd996103fd7e0e4d1d03888e070354b5948769d (patch)
treea8d537981e023d64d46a399031def75df12de15c /src/mainboard
parentfe49f36ca8e084048d8914d8a8eabcf12cc51c9d (diff)
mb/google/rex/var/ovis: Simplify the USB-C port mapping
This patch changes the `EC CONx Mapping` to fix the hot-plug issue where attaching a device to USB-C port C1 can affect the USB-C display over port C2. Note: `PMC MUX Mapping` remains unchanged to reflect the underlying board design where the physical MUX has swapped between C1 and C2 USB-C port. Before: | PMC MUX Mapping | Port C0 | Port C1 | Port C2 | +------------------+-------------+-------------+---------------+ | USB2-Port | 2 | 3 | 1 | | USB3-Port | 0 | 2 | 1 | | EC CONx Mapping | Port C0 | Port C1 | Port C2 | +------------------+-------------+-------------+---------------+ | USB2-Port | 2 | 3 | 1 | | USB3-Port | 0 | 2 | 1 | Physical Mapping between EC and SoC as below: Port C0 - EC CON0 ----> PMC MUX CON0 Port C1 - EC CON1 ----> PMC MUX CON2 Port C2 - EC CON2 ----> PMC MUX CON1 After: | PMC MUX Mapping | Port C0 | Port C1 | Port C2 | +------------------+-------------+-------------+---------------+ | USB2-Port | 2 | 3 | 1 | | USB3-Port | 0 | 2 | 1 | | EC CONx Mapping | Port C0 | Port C1 | Port C2 | +------------------+-------------+-------------+---------------+ | USB2-Port | 2 | 1 | 3 | | USB3-Port | 0 | 1 | 2 | Physical Mapping between EC and SoC as below: Port C0 - EC CON0 ----> PMC MUX CON0 Port C1 - EC CON1 ----> PMC MUX CON1 Port C2 - EC CON2 ----> PMC MUX CON2 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I59e2630bc0f93321cc4b734fcf3c4cf254882477 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/rex/variants/ovis/overridetree.cb16
1 files changed, 8 insertions, 8 deletions
diff --git a/src/mainboard/google/rex/variants/ovis/overridetree.cb b/src/mainboard/google/rex/variants/ovis/overridetree.cb
index 492ab154b2..de86a55ce8 100644
--- a/src/mainboard/google/rex/variants/ovis/overridetree.cb
+++ b/src/mainboard/google/rex/variants/ovis/overridetree.cb
@@ -1,7 +1,7 @@
chip soc/intel/meteorlake
- register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C2
+ register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C1
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0
- register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C1
+ register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C2
register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # Type-A Port A0
register "usb2_ports[6]" = "USB2_PORT_MID(OC3)" # Type-A Port A1
register "usb2_ports[7]" = "USB2_PORT_MID(OC3)" # Type-A Port A2
@@ -98,14 +98,14 @@ chip soc/intel/meteorlake
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(2, 1))"
- device ref tcss_usb3_port2 on end
+ device ref tcss_usb3_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C Port C2""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, LEFT, ACPI_PLD_GROUP(3, 1))"
- device ref tcss_usb3_port1 on end
+ device ref tcss_usb3_port2 on end
end
end
end
@@ -145,14 +145,14 @@ chip soc/intel/meteorlake
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(2, 1))"
- device ref usb2_port3 on end
+ device ref usb2_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-C Port C2""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, LEFT, ACPI_PLD_GROUP(3, 1))"
- device ref usb2_port1 on end
+ device ref usb2_port3 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port A0""
@@ -219,8 +219,8 @@ chip soc/intel/meteorlake
device ref soc_espi on
chip ec/google/chromeec
use conn0 as mux_conn[0]
- use conn1 as mux_conn[2]
- use conn2 as mux_conn[1]
+ use conn1 as mux_conn[1]
+ use conn2 as mux_conn[2]
device pnp 0c09.0 on end
end
end