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| author | Subrata Banik <subratabanik@google.com> | 2022-06-27 16:51:44 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-07-03 04:57:58 +0000 |
| commit | e88bee7219c215120624a07b681a7e0ccc646411 (patch) | |
| tree | 4d4a2907f2124b2061b403b0f2ddf48627b936b4 /src/mainboard | |
| parent | 8206741a062115119a3c005af27c059853a0eafe (diff) | |
soc/intel/meteorlake: Use coreboot native event handler for FSP-M/S
This patch assigns FSP handler event for FSP-M and FSP-S with coreboot
romstage and ramstage debug handler when FSP_USES_CB_DEBUG_EVENT_HANDLER
Kconfig is enabled.
BUG=b:237263080
TEST=Able to build and boot MTL simics. Also, verified the FSP debug
log is using coreboot debug library as below:
Before:
Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE
Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3
Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A
The 0th FV start address is 0x000F961B000, size is 0x00150000, handle
is 0xF961B000
Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38
Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6
With this code change:
[SPEW ] Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE
[SPEW ] Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3
[SPEW ] Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A
[SPEW ] The 0th FV start address is 0x000F95C0000, size is 0x00160000, handle is 0xF95C0000
[SPEW ] Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
[SPEW ] Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38
[SPEW ] Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I80ba73afed642e6d21c5310e9bf734f6f7170347
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/mainboard')
0 files changed, 0 insertions, 0 deletions