soc/amd/picasso: introduce and use chipset device tree

The chipset devicetree only has the essential PCIe devices enabled that
are needed for the SoC code to work. It also defines aliases for all
PCIe devices that can be used to reference the devices in the mainboard-
specific devicetrees and devicetree overrides. To make the change easier
to review that part will be done in a follow-up patch.

Despite missing in the PPR, device pci 18.7 exists on Picasso.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6b7c3fd32579a23539594672593a243172c161c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>

5 files changed, 0 insertions, 92 deletions

diff --git a/src/mainboard/amd/bilby/devicetree.cb b/src/mainboard/amd/bilby/devicetree.cb
index 8adbaa2f50..7015185805 100644
--- a/src/mainboard/amd/bilby/devicetree.cb
+++ b/src/mainboard/amd/bilby/devicetree.cb
@@ -138,18 +138,12 @@ chip soc/amd/picasso
 
 	register "pspp_policy" = "DXIO_PSPP_BALANCED"
 
-	device cpu_cluster 0 on
-		device lapic 0 on end
-	end
 	device domain 0 on
 		subsystemid 0x1022 0x1510 inherit
-		device pci 0.0 on  end # Root Complex
 		device pci 0.2 on  end # IOMMU
-		device pci 1.0 on  end # Dummy Host Bridge
 		device pci 1.1 on  end # GPP Bridge 0
 		device pci 1.2 on  end # GPP Bridge 1
 		device pci 1.5 on  end # NVMe
-		device pci 8.0 on  end # Dummy Host Bridge
 		device pci 8.1 on      # Bridge to Bus A
 			device pci 0.0 on  end # Internal GPU
 			device pci 0.1 on  end # Display HDA
@@ -165,20 +159,10 @@ chip soc/amd/picasso
 			device pci 0.1 off end # integrated Ethernet MAC
 			device pci 0.2 off end # integrated Ethernet MAC
 		end
-		device pci 14.0 on  end # SMBus
 		device pci 14.3 on      # D14F3 bridge
 			chip superio/smsc/sio1036 # optional debug card
 			end
 		end
-		device pci 14.6 off end # SDHCI
-		device pci 18.0 on  end # Data fabric [0-7]
-		device pci 18.1 on  end
-		device pci 18.2 on  end
-		device pci 18.3 on  end
-		device pci 18.4 on  end
-		device pci 18.5 on  end
-		device pci 18.6 on  end
-		device pci 18.7 on  end
 	end # domain
 
 	device mmio 0xfedc9000 on  end # UART0
diff --git a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb
index f82f95851b..d1e0241dcf 100644
--- a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb
+++ b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb
@@ -138,16 +138,10 @@ chip soc/amd/picasso
 
 	register "pspp_policy" = "DXIO_PSPP_BALANCED"
 
-	device cpu_cluster 0 on
-		device lapic 0 on end
-	end
 	device domain 0 on
 		subsystemid 0x1022 0x1510 inherit
-		device pci 0.0 on  end # Root Complex
 		device pci 0.2 on  end # IOMMU
-		device pci 1.0 on  end # Dummy Host Bridge
 		device pci 1.1 on  end # Bridge to PCIe Ethernet chip
-		device pci 8.0 on  end # Dummy Host Bridge
 		device pci 8.1 on      # Bridge to Bus A
 			device pci 0.0 on  end # Internal GPU
 			device pci 0.1 on  end # Display HDA
@@ -163,20 +157,10 @@ chip soc/amd/picasso
 			device pci 0.1 off end # integrated Ethernet MAC
 			device pci 0.2 off end # integrated Ethernet MAC
 		end
-		device pci 14.0 on  end # SMBus
 		device pci 14.3 on      # D14F3 bridge
 			chip superio/smsc/sio1036 # optional debug card
 			end
 		end
-		device pci 14.6 off end # SDHCI
-		device pci 18.0 on  end # Data fabric [0-7]
-		device pci 18.1 on  end
-		device pci 18.2 on  end
-		device pci 18.3 on  end
-		device pci 18.4 on  end
-		device pci 18.5 on  end
-		device pci 18.6 on  end
-		device pci 18.7 on  end
 	end # domain
 
 	device mmio 0xfedc9000 on  end # UART0
diff --git a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb
index c82f38841a..1c2009502d 100644
--- a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb
+++ b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb
@@ -138,16 +138,10 @@ chip soc/amd/picasso
 
 	register "pspp_policy" = "DXIO_PSPP_BALANCED"
 
-	device cpu_cluster 0 on
-		device lapic 0 on end
-	end
 	device domain 0 on
 		subsystemid 0x1022 0x1510 inherit
-		device pci 0.0 on  end # Root Complex
 		device pci 0.2 on  end # IOMMU
-		device pci 1.0 on  end # Dummy Host Bridge
 		device pci 1.3 on  end # Bridge to PCIe Ethernet chip
-		device pci 8.0 on  end # Dummy Host Bridge
 		device pci 8.1 on      # Bridge to Bus A
 			device pci 0.0 on  end # Internal GPU
 			device pci 0.1 on  end # Display HDA
@@ -163,20 +157,10 @@ chip soc/amd/picasso
 			device pci 0.1 off end # integrated Ethernet MAC
 			device pci 0.2 off end # integrated Ethernet MAC
 		end
-		device pci 14.0 on  end # SMBus
 		device pci 14.3 on      # D14F3 bridge
 			chip superio/smsc/sio1036 # optional debug card
 			end
 		end
-		device pci 14.6 off end # SDHCI
-		device pci 18.0 on  end # Data fabric [0-7]
-		device pci 18.1 on  end
-		device pci 18.2 on  end
-		device pci 18.3 on  end
-		device pci 18.4 on  end
-		device pci 18.5 on  end
-		device pci 18.6 on  end
-		device pci 18.7 on  end
 	end # domain
 
 	device mmio 0xfedc9000 on  end # UART0
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
index 252540093c..0d0e8299ca 100644
--- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
+++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
@@ -252,17 +252,10 @@ chip soc/amd/picasso
 
 	register "pspp_policy" = "DXIO_PSPP_POWERSAVE"
 
-	device cpu_cluster 0 on
-		device lapic 0 on end
-	end
-
 	# See AMD 55570-B1 Table 13: PCI Device ID Assignments.
 	device domain 0 on
 		subsystemid 0x1022 0x1510 inherit
-		device pci 0.0 on  end # Root Complex
 		device pci 0.2 on  end # IOMMU
-		device pci 1.0 on  end # Dummy Host Bridge, must be enabled
-		device pci 1.1 off end # GPP Bridge 0
 		device pci 1.2 on      # GPP Bridge 1 - Wifi
 			chip drivers/wifi/generic
 				register "wake" = "GEVENT_8"
@@ -270,9 +263,6 @@ chip soc/amd/picasso
 			end
 		end
 		device pci 1.3 on  end # GPP Bridge 2 - SD
-		device pci 1.4 off end # GPP Bridge 3
-		device pci 1.5 off end # GPP Bridge 4
-		device pci 8.0 on  end # Dummy Host Bridge, must be enabled
 		device pci 8.1 on      # Internal GPP Bridge 0 to Bus A
 			device pci 0.0 on  end # Internal GPU
 			device pci 0.1 on  end # Display HDA
@@ -363,10 +353,6 @@ chip soc/amd/picasso
 			device pci 0.6 off end # HDA
 			device pci 0.7 on  end # non-Sensor Fusion Hub device
 		end
-		device pci 8.2 off     # Internal GPP Bridge 0 to Bus B
-			device pci 0.0 off end # AHCI
-		end
-		device pci 14.0 on  end # SM
 		device pci 14.3 on  # - D14F3 bridge
 			chip ec/google/chromeec
 				device pnp 0c09.0 on
@@ -398,13 +384,6 @@ chip soc/amd/picasso
 				end
 			end
 		end
-		device pci 18.0 on  end # Data fabric [0-7]
-		device pci 18.1 on  end
-		device pci 18.2 on  end
-		device pci 18.3 on  end
-		device pci 18.4 on  end
-		device pci 18.5 on  end
-		device pci 18.6 on  end
 	end # domain
 
 	device mmio 0xfedc5000 on
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
index 89bca93d17..8d0abad076 100644
--- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
+++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
@@ -245,17 +245,10 @@ chip soc/amd/picasso
 
 	register "pspp_policy" = "DXIO_PSPP_POWERSAVE"
 
-	device cpu_cluster 0 on
-		device lapic 0 on end
-	end
-
 	# See AMD 55570-B1 Table 13: PCI Device ID Assignments.
 	device domain 0 on
 		subsystemid 0x1022 0x1510 inherit
-		device pci 0.0 on  end # Root Complex
 		device pci 0.2 on  end # IOMMU
-		device pci 1.0 on  end # Dummy Host Bridge, must be enabled
-		device pci 1.1 off end # GPP Bridge 0
 		device pci 1.2 on      # GPP Bridge 1 - Wifi
 			chip drivers/wifi/generic
 				register "wake" = "GEVENT_8"
@@ -263,11 +256,7 @@ chip soc/amd/picasso
 			end
 		end
 		device pci 1.3 on  end # GPP Bridge 2 - SD
-		device pci 1.4 off end # GPP Bridge 3
-		device pci 1.5 off end # GPP Bridge 4
-		device pci 1.6 off end # GPP Bridge 5
 		device pci 1.7 on  end # GPP Bridge 6 - NVME
-		device pci 8.0 on  end # Dummy Host Bridge, must be enabled
 		device pci 8.1 on      # Internal GPP Bridge 0 to Bus A
 			device pci 0.0 on  end # Internal GPU
 			device pci 0.1 on  end # Display HDA
@@ -385,10 +374,6 @@ chip soc/amd/picasso
 			device pci 0.6 off end # HDA
 			device pci 0.7 on  end # non-Sensor Fusion Hub device
 		end
-		device pci 8.2 off     # Internal GPP Bridge 0 to Bus B
-			device pci 0.0 off end # AHCI
-		end
-		device pci 14.0 on  end # SM
 		device pci 14.3 on  # - D14F3 bridge
 			chip ec/google/chromeec
 				device pnp 0c09.0 on
@@ -434,14 +419,6 @@ chip soc/amd/picasso
 				end
 			end
 		end
-		device pci 14.6 off end # Non-Functional SDHCI
-		device pci 18.0 on  end # Data fabric [0-7]
-		device pci 18.1 on  end
-		device pci 18.2 on  end
-		device pci 18.3 on  end
-		device pci 18.4 on  end
-		device pci 18.5 on  end
-		device pci 18.6 on  end
 	end # domain
 
 	chip drivers/generic/max98357a