sb/intel/i82801jx: Add common code for LPC decode

Change-Id: Id706da33f06ceeec39ea50301130770226f0474e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

8 files changed, 17 insertions, 39 deletions

diff --git a/src/mainboard/asus/p5qc/romstage.c b/src/mainboard/asus/p5qc/romstage.c
index fb30beeffb..3462a3d99d 100644
--- a/src/mainboard/asus/p5qc/romstage.c
+++ b/src/mainboard/asus/p5qc/romstage.c
@@ -51,19 +51,6 @@ static void mb_gpio_init(void)
 	RCBA32(0x3f00) = 0x00000038;
 }
 
-static void ich10_enable_lpc(void)
-{
-	/* Configure serial IRQs.*/
-	pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010);
-	pci_write_config16(LPC_DEV, D31F0_LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN
-			   | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN
-			   | COMA_LPC_EN);
-	/* HW EC */
-	pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x00000295);
-	/* ????? */
-	pci_write_config32(LPC_DEV, D31F0_GEN2_DEC, 0x001c4701);
-}
-
 void mainboard_romstage_entry(void)
 {
 	const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 };
@@ -71,7 +58,7 @@ void mainboard_romstage_entry(void)
 	u8 s3_resume;
 
 	/* Set southbridge and Super I/O GPIOs. */
-	ich10_enable_lpc();
+	i82801jx_lpc_setup();
 	mb_gpio_init();
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
diff --git a/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb
index 6e0a40a651..fb818ffa7f 100644
--- a/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb
+++ b/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb
@@ -45,6 +45,9 @@ chip northbridge/intel/x4x		# Northbridge
 			# Enable PCIe ports 0,2,3 as slots.
 			register "pcie_slot_implemented"	= "0x31"
 
+			register "gen1_dec" = "0x00000295"
+			register "gen2_dec" = "0x001c4701"
+
 			device pci 19.0 off end		# GBE
 			device pci 1a.0 on end		# USB
 			device pci 1a.1 on end		# USB
diff --git a/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb
index 902dcfdcb5..d89f5cc645 100644
--- a/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb
+++ b/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb
@@ -45,6 +45,9 @@ chip northbridge/intel/x4x		# Northbridge
 			# Enable PCIe ports 0,2,3 as slots.
 			register "pcie_slot_implemented"	= "0x31"
 
+			register "gen1_dec" = "0x00000295"
+			register "gen2_dec" = "0x001c4701"
+
 			device pci 19.0 off end		# GBE
 			device pci 1a.0 on end		# USB
 			device pci 1a.1 on end		# USB
diff --git a/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb
index c596a42244..0428b50e9a 100644
--- a/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb
+++ b/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb
@@ -45,6 +45,9 @@ chip northbridge/intel/x4x		# Northbridge
 			# Enable PCIe ports 0,2,3 as slots.
 			register "pcie_slot_implemented"	= "0x31"
 
+			register "gen1_dec" = "0x00000295"
+			register "gen2_dec" = "0x001c4701"
+
 			device pci 19.0 off end		# GBE
 			device pci 1a.0 on  end		# USB
 			device pci 1a.1 on  end		# USB
diff --git a/src/mainboard/asus/p5ql-em/devicetree.cb b/src/mainboard/asus/p5ql-em/devicetree.cb
index 165340321b..fd0b1034af 100644
--- a/src/mainboard/asus/p5ql-em/devicetree.cb
+++ b/src/mainboard/asus/p5ql-em/devicetree.cb
@@ -49,6 +49,8 @@ chip northbridge/intel/x4x		# Northbridge
 			# Enable PCIe ports 0,1,3,4,5 as slots.
 			register "pcie_slot_implemented"	= "0x3b"
 
+			register "gen1_dec" = "0x00000295"
+
 			device pci 19.0 off end		# GBE
 			device pci 1a.0 on		# USB
 				subsystemid 0x1043 0x82d4
diff --git a/src/mainboard/asus/p5ql-em/romstage.c b/src/mainboard/asus/p5ql-em/romstage.c
index 614f4874e1..142ee73e49 100644
--- a/src/mainboard/asus/p5ql-em/romstage.c
+++ b/src/mainboard/asus/p5ql-em/romstage.c
@@ -117,16 +117,6 @@ static void mb_gpio_init(void)
 	RCBA8(0x31ff);
 }
 
-static void ich10_enable_lpc(void)
-{
-	/* Configure serial IRQs.*/
-	pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010);
-	pci_write_config16(LPC_DEV, D31F0_LPC_EN, CNF1_LPC_EN | KBC_LPC_EN
-			   | FDD_LPC_EN | LPT_LPC_EN | COMA_LPC_EN);
-	/* Hardware monitor IO range */
-	pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x00000295);
-}
-
 void mainboard_romstage_entry(void)
 {
 	/* This board has first dimm slot of each channel hooked up to
@@ -138,7 +128,7 @@ void mainboard_romstage_entry(void)
 	u8 s3_resume;
 
 	/* Set southbridge and Super I/O GPIOs. */
-	ich10_enable_lpc();
+	i82801jx_lpc_setup();
 	mb_gpio_init();
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 
diff --git a/src/mainboard/intel/dg43gt/devicetree.cb b/src/mainboard/intel/dg43gt/devicetree.cb
index be0b911a5a..38ae29b031 100644
--- a/src/mainboard/intel/dg43gt/devicetree.cb
+++ b/src/mainboard/intel/dg43gt/devicetree.cb
@@ -42,6 +42,9 @@ chip northbridge/intel/x4x		# Northbridge
 			# Enable PCIe ports 0,2,3 as slots.
 			register "pcie_slot_implemented"	= "0xb"
 
+			register "gen1_dec" = "0x00fc0601"
+			register "gen2_dec" = "0x00fc0291"
+
 			device pci 19.0 on end		# GBE
 			device pci 1a.0 on end		# USB
 			device pci 1a.1 on end		# USB
diff --git a/src/mainboard/intel/dg43gt/romstage.c b/src/mainboard/intel/dg43gt/romstage.c
index 018df1bedf..6e645b5630 100644
--- a/src/mainboard/intel/dg43gt/romstage.c
+++ b/src/mainboard/intel/dg43gt/romstage.c
@@ -53,19 +53,6 @@ static void mb_gpio_init(void)
 	RCBA32(0x3f00) = 0x0000000b;
 }
 
-static void ich10_enable_lpc(void)
-{
-	/* Configure serial IRQs.*/
-	pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010);
-	pci_write_config16(LPC_DEV, D31F0_LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN
-			   | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN
-			   | GAMEL_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
-			   | COMB_LPC_EN | COMA_LPC_EN);
-	pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0xfc0601);
-	pci_write_config32(LPC_DEV, D31F0_GEN2_DEC, 0xfc0291);
-	pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0);
-}
-
 void mainboard_romstage_entry(void)
 {
 	const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 };
@@ -73,7 +60,7 @@ void mainboard_romstage_entry(void)
 	u8 s3_resume;
 
 	/* Set southbridge and Super I/O GPIOs. */
-	ich10_enable_lpc();
+	i82801jx_lpc_setup();
 	mb_gpio_init();
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);